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What is Test-Logic-Reset State?

At the test-logic-reset controller state, the test logic is disabled so that normal operation of the boundary scan device can proceed unhindered. The instruction register is initialized to contain the IDCODE instruction if the device contains the optional identification register or the BYPASS instruction. Regardless of the TAP controller state, it will enter test-logic-reset when test mode select (TMS) is held high for at least five rising edges of the test clock (TCK), or when the optional test reset pin (TRST) is asserted. The TAP controller remains in this state while TMS is high.