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What is IEEE Standard 1581?

The IEEE Standard (Std) 1581 is the standard for Static Component Interconnection Test Protocol and Architecture. The IEEE Std 1581 targets testing for low-cost, complex DDR memory devices, which would be able to communicate through another semiconductor device with an IEEE Std 1149.1 boundary scan capability.

Presently, even if double data rate (DDR) memory devices adopt the IEEE 1149.1 boundary scan standard, this is still not a feasible test, as it will require the addition of the four mandatory test access port (TAP) pins to the DDR device, which would add to the complexity and cost of the device.

IEEE Std 1581 provides the protocol to access the test mode within the memory devices, without the need for dedicated test pin requirements. The defined standard for this new test technology would enable each vendor to create its own method for implementing test hardware functionality in memory devices. It guides them on the necessary implementation rules for access and exit test modes.

In contrast to IEEE Std 1149.1, this standard provides a static test method and requires fewer test pins. The standard also allows for implementation of IEEE Std 1581 on other semiconductor devices besides memory devices.

The benefit of IEEE Std 1581 is that it helps the DDR memory vendor enable memory devices to communicate with boundary scan-enabled devices. Manufacturers can regain the test coverage on DDR memory devices that even current standalone solutions like IEEE Std 1149.1 are finding hard to run with any good measure of stability due to high clock speeds.

Figure 1: IEEE Std 1581 memory device connected to IEEE Std 1149.1 device.