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Digital Design & Interconnect Standards

In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Keysight - Insights for your best design

Learn more about Digital Design & Interconnect solutions from Keysight. 

Keysight RF and Digital Learning Center - A commitment to learning with industry experts 
 

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B4621B Bus Decoder for DDR2, DDR3, or DDR4 Debug and Validation - Data Sheet 
The B4621B protocol-decode software translates acquired signals into easily understood bus transactions showing associated data bursts for double- edge data-rate captures up to 2.5 Gb/s.

Data Sheet 2017-02-21

PDF PDF 1.10 MB
DDR3 Memory Protocol Analysis and Compliance Verification – FuturePlus 
Straightforward and reliable DDR3 DIMM bus analysis at 2400MT/s and DDR3 SO-DIMM analysis at 1867MT/s – FuturePlus System and Keysight

Solution Brief 2015-07-14

 
DDR4 Protocol Analysis - FuturePlus 
DDR4 Protocol Analysis from FuturePlus and Keysight.

Solution Brief 2015-06-30

 
DisplayPort 1.2 Link Layer Testing - FuturePlus 
DisplayPort 1.2 Link Layer Testing Solution from FuturePlus and Keysight.

Solution Brief 2015-06-30

 
Soft Touch Connectorless Logic Analyzer Probes - Application Notes 

Application Note 2015-05-20

HDMI and DisplayPort Design and Test – A Better Way - Brochure 
Brochure covering Keysight’s HDMI and Displayport test solutions portfolio and applications, discussing measurement challenges and showing how the test solutions and services address these.

Brochure 2015-01-23

PDF PDF 11.70 MB
Tips for Making Better Memory Measurements – Video Series 
Videos that show customers how perform a comprehensive, unique and extensive analysis in less time.

Demo 2013-03-18

 
DDR Memory Design and Test Overview  
Brief overview of Keysight solutions for DDR design and test.

Brochure 2012-12-19

PDF PDF 1.14 MB
DDR Memory Design and Test – A Better Way 
Keysight offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.

Brochure 2012-12-19

PDF PDF 5.17 MB
B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation - Data Sheet 
The B4623B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for LPDDR, LPDDR2, LPDDR3 at full bus data rates.

Data Sheet 2012-09-03

PDF PDF 1.03 MB
MIPI D-PHY Protocol Test Solutions  
N4851A/B MIPI D-PHY Acquisition Probe, and N4861A/B MIPI D-PHY Stimulus Probe

Data Sheet 2009-10-02

Using the Keysight Infiniium Series Real-time Oscilloscope to Validate the DigRF 
The DigRF v3 standard presents new digital hardware validation challenges for mobile wireless development as the links between the baseband (BB) ICs and the radio frequency (RF) ICs transition from an analog interface to a digital interface.

Application Note 2009-05-27

10 Reasons to Upgrade to a 16800 or 16900 Series Logic Analyzer 
10 Reasons to Upgrade to a 16800 or 16900 Series Logic Analyzer

Application Note 2007-12-03

Keysight Solutions for the DigRF v3 Digital Serial Interface Used In Mobile Wireless Devices 
Rapidly deploy your DigRF v3-based designs using Keysight logic analyzer and RF tools for stimulus and analysis in the digital and RF domains.

Brochure 2007-01-30

PDF PDF 521 KB
16900 Series Modular Logic Analyzers Video 
16900 Series Logic Analyzer Video

Demo 2006-11-01

Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems 
Application Note 1575

Application Note 2006-04-14

Passively Probing an InfiniBand System with a Keysight 16700 Series Logic Analysis System 
Passively Probing an InfiniBand with Keysight 16700 Series Logic Analysis System

Application Note 2004-03-05

PDF PDF 588 KB
8 Hints for Debugging and Validating High-speed Buses 
8 Hints for Debugging High-speed Buses

Application Note 2002-03-05

PDF PDF 2.24 MB
Designing and Validating High-Speed Memory Buses (AN 1382-2) 
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...

Application Note 2001-12-20