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PCI Express® (PCIe) Design & Test

Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI. 

PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth. 

PCIe 4.0 at 16 GT/s doubles data rates again, requiring extensive testing and validation to enable speed, while maintaining backward compatibility with earlier generations.

Regardless of the generation of PCIe design you are testing or the PCI Express design challenges you are facing, Keysight offers a complete solution set from design to test. Work with Keysight and gain insights for you best PCIe design.


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See measurement solution examples to discover specific solutions for your PCIe needs

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USB 3.1 10G Type-C Receiver Testing - video 
How do you test a USB 3.1 gen2 10G Type-C receiver? It can be very complex. This video provides an overview of intrinsic jitter requirements, automated calibration options, getting your device into loopback mode, and more!

Demo 2016-01-25

 
PCI Express® Design and Test from Electrical to Protocol - Brochure 
This brochure provides insight into how to thoroughly simulate, characterize and validate PCI Express Designs.

Brochure 2015-08-17

PDF PDF 4.78 MB
PCI Express Receiver Testing Responds To New Challenges - Article 
PCI Express Receiver Testing Responds To New Challenges

Article 2015-03-24

 
Digital Design & Interconnect Standards - Brochure 
Brochure shows Keysight’s high-speed digital solution set , a range of essential tools, measurement and simulation—that will help cut through the challenges of gigabit digital designs.

Brochure 2015-03-09

PDF PDF 7.71 MB
PCI Express Transmitter Electrical Validation and Compliance Testing - Application Note 
This application note is intended for digital designers and developers validating electrical performance of PCI Express-based designs and working toward electrical compliance of PCI Express products.

Application Note 2011-10-28

PDF PDF 1.01 MB
PCI Express® Revision 2 - Receiver Testing With J-BERT N4903A and 81150A Pulse - Application Note 
Receiver Testing With J-BERT N4903A and 81150A Pulse

Application Note 2008-12-03

PDF PDF 1000 KB
Upgrade to PCI Express 2.0© Receiver Test - Application Note 
The 15431A is a filter set for the 81150A. It generates the random jitter profile for testing PCI Express 2.0 receivers, to be used in conjunction with the N4903A. This fact sheet explains the upgrade.

Application Note 2008-10-24

PDF PDF 348 KB
Jitter Solutions for Telecom, Enterprise, and Digital Designs - Brochure 
Complete solutions for characterization and test of jitter in high-speed digital transmission systems, high-speed I/O connections, and buses.

Brochure 2008-06-25

PDF PDF 3.49 MB
BERT Application Brochure 
Answers for your multi-gigabit test challenges

Brochure 2007-01-15

PDF PDF 1.37 MB
PCI Express Receiver Design Validation Test with 81134A / 81250A - Application Note 
Describes functional validation and compliance and stress tests for PCI Express receiver design

Application Note 2005-03-18