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Mastering Signal and Power Integrity Design Challenges for DDR and Gen5 Applications
The Most Complete Design Flow from EDA-to-Test
Increasing bandwidth and cache memory leads to a growing pressure to accelerate the design-to-market times for complex DDR-4 and soon DDR-5 DRAM technology. Hardware designers, working on memory systems, are facing both shrinking timing and voltage margins, and a complex list of compliance measurements. As we move to DDR4, random jitter becomes much more significant and the designer needs to have confidence they can pass the Receiver Mask Tests at ultra-low Bit Error Rates.
This hands-on workshop gives you a deeper insight into a unique design flow from EDA to test, guiding users through industry-leading, traceable measurements. Keysight’s PathWave Advance Design System Memory Designer offers a workflow that minimises efforts required to setup, extract EM models, simulate the buses, and perform compliance testing. Offering the same measurement science for both simulation and hardware verification stages makes it easy to compare the two. Different probing techniques will be covered for both single-ended and differential modes. Understand how higher data rates and better power efficiency affect voltage/timing margins. Learn the importance of measuring Jitter accurately.
WHO SHOULD ATTEND
Designers that need to implement and verify the setup and performance of DDR memory buses at the latest data rates.
COST
Complimentary
Time
09:15 – 16:15 (CET)
LOCATION
Italy
Dates and Locations
Wednesday, June 19, 2019
Rome, Italy
Thursday, June 20, 2019
Milan, Italy
Agenda
09:15 – Registration and Welcome
09:45 – Designing High Speed Serial Buses
11:00 – Challenges Designing for DDR4 and Beyond
12:00 – Gen5 Revolution of High-Speed Digital Bus Standards: Implications for Testing and Validation?
13:00 – Lunch
14:00 – Addressing Power Integrity and Crosstalk Issues on Mixed Signal PCB
15:00 – A Real-Life Example (External Speaker)
15:30 – Electrothermal PCB Simulations
16:00 – Wrap-up
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