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PCI Express (PCIe®)
Catch the latest insights in PCIe 6.0 design-to-test workflows from the industry's foremost experts.
Ensure PCIe success, from simulation to protocol test, with the most complete PCI Express® 6.0 solution. Keysight is a major contributor to the PCI-SIG® primary working groups and has been since their inception. We help you navigate through complex requirements with unmatched expertise and world-leading support. Keysight helps you improve time to market and streamline your path to PCIe success with scalable solutions.
PCIe Design-to-Test Solutions
Select the workflow stage below to learn about Keysight's end-to-end PCIe design and test solutions.
Design Simulation
The design of high-speed serial data links becomes significantly more complex as data rates increase — channel topologies become more diverse, and the number of parameters that need to be tuned for active components multiply. You need to use simulation to optimize the signal and power integrity of your PCIe designs and analyze the electromagnetic (EM) effects of components such as high-speed integrated circuit (IC) packages and printed circuit board (PCB) interconnects. We can help you quickly and effectively evaluate the end-to-end performance of your PCIe 6.0 links.
Transmitter Compliance Testing
PCI Express 6.0 is a revolutionary step with challenges never seen before, a move from NRZ to PAM4 with an eye height of only 6mV vs. 15 mV in PCI Express 5.0. To accurately measure eye heights as small as 6 mV you need the world’s best scope noise performance.
Our leading-edge transmitter test automation tools, developed by Keysight experts, ensure the integrity of your PCIe measurements, avoid costly redesigns and improve your time to market.
Receiver Compliance Testing
Extracting digital content from the PCIe signal is significantly more challenging with the PAM4 format and PCIe speeds reaching up to 64 GT/s. At these high data transfer rates with PAM4 signals, PCIe receivers often receive a heavily degraded signal due to the channel’s high-frequency loss characteristics, resulting in unacceptable bit error ratios (BERs). Bit errors are handled with forward error correction (FEC); new measurements are required like signal-to-noise and distortion ratio (SNDR).
Protocol Validation
Protocol validation occurs at the physical, data link, and transaction layers. In addition to the mandatory protocol compliance tests, the PCI-SIG recommends more than a hundred additional tests to characterize your design correctly. A key area of protocol test is link training and status state machine (LTSSM) to determine if data packets are reliably transferred between link partners. You need protocol analysis and exerciser tools to determine if your PCIe device can successfully communicate with its link partner. We can help you perform complex PCIe 5.0 and 6.0 protocol tests and quickly debug any detected errors to ensure compliance with your PCIe devices.
Additional PCIe Resources
PCI-SIG®, PCIe® and PCI Express® are US registered trademarks and/or service marks of PCI-SIG.
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