Advanced Design System (ADS) 2016 is the next major step in delivering new capabilities, new technologies and more improvements to further realize a long-term vision of improving design productivity and efficiency through design flow integration.

SIPro and PIPro Products for Signal Integrity and Power Integrity analysis

ADS 2016 redefines the Signal Integrity (SI) and Power Integrity (PI) workflow for high-speed digital design. The new workflow within ADS introduces two new product features, SIPro and PIPro for ADS 2016. SIPro and PIPro share a single environment and deliver high-accuracy EM results in a much faster simulation time than general purpose EM solvers. The new cohesive workflow enables the user to perform both SI and PI analyses on a common design. The EM setup is ‘net-driven’, enabling the user to quickly navigate large and densely routed boards, and include only the nets that they wish to simulate (specific signal nets, power nets, ground nets); No time wasted in manual layout editing, no need to remove unwanted layout details before simulation. From the new dedicated user interface, users can view the board design natively in 3D, easily copy EM-setups from one analysis type to another, simulate, visualize the results then automatically generate schematics ready for further circuit simulation and parameter tuning.

SIPro uses an innovative composite EM technology to provide both Speed and Accuracy. The technology is a pure-EM solution, and all significant EM effects like via-to-via coupling, via to trace transitions, and losses due to imperfect ground returns paths, are taken into account. Simulation results approach gold-standard 3D-FEM to 20GHz and beyond, but in a fraction of the simulation time.

PIPro is a series of 3 dedicated EM solvers for analyzing Power Delivery Networks (PDNs) on a Printed Circuit Board (PCB). Analyses include:

• DC IR drop Analysis
• AC PDN Impedance Analysis
• Power Plane Resonances Analysis

Once the simulation has completed, the models for decoupling capacitors, inductors and resistors can be changed, and the simulation results will automatically update, without requiring an EM re-simulation. A schematic test bench for the PDN can be automatically created, allowing tuning of the components and detailed behavioral modeling of the Voltage Regulator Module (VRM).

Improved Harmonic Balance and Circuit Envelope simulation

ADS 2016 continues to advance circuit simulation technology through enhancements to its Harmonic Balance and Circuit Envelope simulators improving speed, convergence and accuracy. Additionally, enhanced DC annotation speeds are equipped for even the most complex designs.

Electro-Thermal Simulation for Windows

The Electro-Thermal simulator is now fully supported on Windows as well as Linux making it more accessible to more designers. 

Momentum EM Simulation

The Momentum 3D planar EM simulator now includes parameterized substrates for EM simulations that enable designers to model process variability. TSMC iRCX import support and Via simplification & Simulation of Dummy Metal Fills are also included in this release.

Layout and Layout Verification

Numerous enhancements and new capabilities make ADS Layout, faster, more intuitive and manufacturing robust. A few of the new additions include, manufacturing grid enforcement, improvements to ground nets, faster 3D viewer, improved highlighting, connectivity, mapping layout nets to schematic net names, as well as importing .brd files for EM simulation. 

Silicon RFIC

ADS 2016 brings an array of improvements to the RFIC silicon design front-end flow. Through the build-out of OpenAccess interoperability in ADS 2016, it is now possible to perform the schematic design of a silicon RFIC in ADS using a Virtuoso like DC annotation, improved schematic functionality, usability and support for config views to switch between simulation views. In interoperability, the designer works off a single OpenAccess design library that stays synchronized between the EDA platforms, removing redundant steps of porting and translating design blocks. While this makes ADS an attractive alternative for the schematic frontend design of silicon RFICs, it also enables a true co-simulation at the chip level of circuit RF blocks partitioned between Spice circuit models and interconnects, or at the module chip level across silicon chip and package or laminate using ADS industry leading 3D EM tools of MoM, FEM and FDTD. The co-simulation process unlocks new levels of simulation fidelity, enabling the designer to achieve first time silicon success by accurately predicting rf-circuit performance in the presence of physical layout and process variation effects. Use ADS 2016 to design and optimize entire RF-cores or RF-chips, add dummy metal fills hierarchically in an rf-aware manner and validate with a Momentum simulation the effect of dummy fills and process variation prior to tape-out.

The layout views that are required for the EM simulation are generated from Virtuoso using the ExpressPcell feature. In addition to the interoperability between ADS and Virtuoso, ADS 2016 also supports IPL Alliance based interoperable iPDKs. Using either design flow whether through ADS/Virtuoso interoperability or through IPL Alliance iPDK, the designer benefits from the build-out of the OpenAccess interoperability.

ADS 2016 Silicon RFIC support includes:

• A steadily growing number of interoperable PDKs. Currently 20+ PDKs from various foundries are available.
• Interoperability between ADS/Virtuoso and IPL Alliance iPDKs
• Schematic interoperability with Virtuoso like DC annotation, config views, schematic pcells, VerilogA
• New Momentum RFIC permitting efficient simulation of entire RF cores
  • smart merging of via arrays
  • fast simulation of dummy metal fill
  • substrate parametrization to explore effect of process variation and sensitivity
  • circuit partitioning between Spice models and interconnect EM simulation
  • reads OA access layout via ExpressPcell for Virtuoso CDF pcells or Synopsys PyCell for IPL iPDKs
  • generate substrate files “on the fly” from iRCX based TSMC technology file
• Dummy metal fill utility
  • create dummy metal fill hierarchically in an rf-aware manner on entire RF chips and use within ADS or other OA EDA platforms for design sign-off

Wireless Libraries

The new W2383EP/ET 5G Advanced Modem for ADS enables the design and verification of designs for the emerging 5G wireless standards. This wireless library contains pre-configured simulation setups with modulated sources and demodulation that comply fully with wireless specifications. The signal generation and demodulation algorithms are fully consistent with Keysight instrumentation to bring instrument-level compliance and accuracy into your circuit simulation and verification results. Keysight’s 5G Wireless Library will always be first to emerge along with the latest standards because of our active participation in the standards-setting committees, which is critical for timely instrumentation design and development.

The W2385EP/ET Wireless Networking Verification Test Bench has been updated to include Wireless Networking (BTLE 4.0).

Additional New Capabilities in ADS 2016

• IBIS-AMI Based PAM-4 Link Simulation
• Mix-match AMI Tx/Rx & non-AMI Rx/Tx in Channel Sim
• Dependency resolution in AMI models
• Enhancements to AMI on-die S-parameter models
• PRBS Source enhancements
• New SnP component
• S-parameter viewer
• New TermG component
• Front panel SP-TDR
• IBIS package modeling
• IBIS overclocking in power-aware models
• IBIS 6.0 parser with extensions

View other ADS Product Versions.

Learn more about Keysight Advanced Design System (ADS)