!!!!    6    0    1  991763095  V81d3                                         

! Device           : 74ls594
! Function         : 8 bit shift registar with output latches
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle  1u
receive delay 900n

assign   VCC         to pins  16
assign   GND         to pins  8


assign   RCLRbar    to pins  13
assign   RCK         to pins  12
assign   SCLRbar     to pins  10
assign   SCK         to pins  11
assign   SER         to pins  14

assign   Qh_Qa       to pins  7,6,5,4,3,2,1,15
assign   Qh_Qa0      to pins  15           !AT Added for minimum pin test.
assign   Qh_Qa1      to pins   1           !AT Added for minimum pin test.
assign   Qh_Qa2      to pins   2           !AT Added for minimum pin test.
assign   Qh_Qa3      to pins   3           !AT Added for minimum pin test.
assign   Qh_Qa4      to pins   4           !AT Added for minimum pin test.
assign   Qh_Qa5      to pins   5           !AT Added for minimum pin test.
assign   Qh_Qa6      to pins   6           !AT Added for minimum pin test.
assign   Qh_Qa7      to pins   7           !AT Added for minimum pin test.

assign   Qh9         to pins  9

family    TTL

power          VCC,GND

inputs         RCLRbar, RCK, SCLRbar, SCK, SER

outputs        Qh_Qa, Qh9
outputs  Qh_Qa0, Qh_Qa1, Qh_Qa2, Qh_Qa3  !AT Added for minimum pin test.
outputs  Qh_Qa4, Qh_Qa5, Qh_Qa6, Qh_Qa7  !AT Added for minimum pin test.

trace Qh_Qa, Qh9 to RCLRbar, RCK, SCLRbar, SCK, SER
!***************************************************************
!***************************************************************

vector   Reset
      set   RCLRbar  to "1"
      set   RCK      to "0"
      set   SCLRbar  to "0"
      set   SCK      to "0"
      set   SER      to "0"
end vector

vector   Keep_Control
      set   RCLRbar  to "k"
      set   RCK      to "k"
      set   SCLRbar  to "k"
      set   SCK      to "k"
      set   SER      to "k"
end vector

vector   RCLRbar_low
      initialize to Keep_Control
      set   RCLRbar  to "0"
end vector

vector   Clock_high
      initialize to Keep_Control
      set   RCK      to "1"
      set   SCK      to "1"
end vector

vector   Clock_low
      initialize to Keep_Control
      set   RCK      to "0"
      set   SCK      to "0"
end vector

vector   SER_high
      initialize to Keep_Control
      set   SER  to "1"
end vector

vector   SER_low
      initialize to Keep_Control
      set   SER  to "0"
end vector

vector   SCLRbar_high
      initialize to Keep_Control
      set   SCLRbar  to "1"
end vector

vector   SCLRbar_low
      initialize to Keep_Control
      set   SCLRbar  to "0"
end vector

vector   Qh_Qa_01010101
      initialize to Keep_Control
      set   Qh_Qa    to "01010101"
end vector

vector   Qh_Qa_10101010
      initialize to Keep_Control
      set   Qh_Qa    to "10101010"
end vector

vector   Qh_Qa_00000000
      initialize to Keep_Control
      set   Qh_Qa    to "00000000"
end vector

vector   Qh9_high
      initialize to Keep_Control
      set   Qh9      to "1"
end vector

vector   Qh9_low
      initialize to Keep_Control
      set   Qh9      to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  Qh_Qa0_0
   initialize     to Keep_Control
   set   Qh_Qa0   to "0"
end vector

vector  Qh_Qa0_1
   initialize     to Keep_Control
   set   Qh_Qa0   to "1"
end vector

vector  Qh_Qa1_0
   initialize     to Keep_Control
   set   Qh_Qa1   to "0"
end vector

vector  Qh_Qa1_1
   initialize     to Keep_Control
   set   Qh_Qa1   to "1"
end vector

vector  Qh_Qa2_0
   initialize     to Keep_Control
   set   Qh_Qa2   to "0"
end vector

vector  Qh_Qa2_1
   initialize     to Keep_Control
   set   Qh_Qa2   to "1"
end vector

vector  Qh_Qa3_0
   initialize     to Keep_Control
   set   Qh_Qa3   to "0"
end vector

vector  Qh_Qa3_1
   initialize     to Keep_Control
   set   Qh_Qa3   to "1"
end vector

vector  Qh_Qa4_0
   initialize     to Keep_Control
   set   Qh_Qa4   to "0"
end vector

vector  Qh_Qa4_1
   initialize     to Keep_Control
   set   Qh_Qa4   to "1"
end vector

vector  Qh_Qa5_0
   initialize     to Keep_Control
   set   Qh_Qa5   to "0"
end vector

vector  Qh_Qa5_1
   initialize     to Keep_Control
   set   Qh_Qa5   to "1"
end vector

vector  Qh_Qa6_0
   initialize     to Keep_Control
   set   Qh_Qa6   to "0"
end vector

vector  Qh_Qa6_1
   initialize     to Keep_Control
   set   Qh_Qa6   to "1"
end vector

vector  Qh_Qa7_0
   initialize     to Keep_Control
   set   Qh_Qa7   to "0"
end vector

vector  Qh_Qa7_1
   initialize     to Keep_Control
   set   Qh_Qa7   to "1"
end vector

!***************************************************************
!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with Qh_Qa0.

unit "awaretest Qh_Qa0 Test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa0_0

      execute  SER_high
      repeat 8 times
         execute  Clock_high
         execute  Clock_low
      end repeat
      execute  Qh_Qa0_1
end   unit

unit "awaretest Qh_Qa1 Test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa1_0

      execute  SER_high
      repeat 8 times
         execute  Clock_high
         execute  Clock_low
      end repeat
      execute  Qh_Qa1_1
end   unit

unit "awaretest Qh_Qa2 Test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa2_0

      execute  SER_high
      repeat 8 times
         execute  Clock_high
         execute  Clock_low
      end repeat
      execute  Qh_Qa2_1
end   unit

unit "awaretest Qh_Qa3 Test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa3_0

      execute  SER_high
      repeat 8 times
         execute  Clock_high
         execute  Clock_low
      end repeat
      execute  Qh_Qa3_1
end   unit

unit "awaretest Qh_Qa4 Test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa4_0

      execute  SER_high
      repeat 8 times
         execute  Clock_high
         execute  Clock_low
      end repeat
      execute  Qh_Qa4_1
end   unit

unit "awaretest Qh_Qa5 Test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa5_0

      execute  SER_high
      repeat 8 times
         execute  Clock_high
         execute  Clock_low
      end repeat
      execute  Qh_Qa5_1
end   unit

unit "awaretest Qh_Qa6 Test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa6_0

      execute  SER_high
      repeat 8 times
         execute  Clock_high
         execute  Clock_low
      end repeat
      execute  Qh_Qa6_1
end   unit

unit "awaretest Qh_Qa7 Test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa7_0

      execute  SER_high
      repeat 8 times
         execute  Clock_high
         execute  Clock_low
      end repeat
      execute  Qh_Qa7_1
end   unit

!****************************************************************

unit  "test1"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa_00000000

      repeat 4 times
      execute  SER_high
      execute  Clock_high
      execute  Clock_low

      execute  SER_low
      execute  Clock_high
      execute  Clock_low
      end repeat
      execute  Qh_Qa_01010101
      execute  Qh9_high

      execute  SER_low
      execute  Clock_high
      execute  Clock_low
      execute  Qh_Qa_10101010
      execute  Qh9_low

      execute  SCLRbar_low
      execute  Clock_high
      execute  Clock_low
      execute  Clock_high
      execute  Clock_low
      execute  Clock_high
      execute  Qh_Qa_00000000
end   unit



unit  "Clear (RCLRbar) test"
      execute  Reset
      execute  SCLRbar_high
      execute  Qh_Qa_00000000

      repeat 4 times
      execute  SER_high
      execute  Clock_high
      execute  Clock_low

      execute  SER_low
      execute  Clock_high
      execute  Clock_low
      end repeat
      execute  Qh_Qa_01010101
      execute  RCLRbar_low
      execute  Qh_Qa_00000000
end unit

!End of test

