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Now available on-demand
Keynote: Scaling HPC SoC Designs in the Era of AI with Silicon IP
Learn the silicon IP market trends in high-performance computing system-on-chip designs and how to achieve your latency, power, and bandwidth goals.
Prepare to Test and Avoid Pitfalls in USB4 Implementations
Prepare to test next-generation USB Type-C® technologies with the right test methodologies.
Data Center Technologies Move Toward $1 per Gigabit
Understand how next-generation data center technologies help the industry to drastically reduce the cost of data center interconnects.
On-Wafer / Die Test for Photonic Integrated Circuits
Effective and fast optical and electro-optical wafer and die level testing with surface and edge coupling.
Improve Device Performance Using Power Integrity Test Tools
Understand common Power Integrity and PMIC design issues. Improve test accuracy and efficiency by adopting the latest Power Integrity techniques.
Test & Measurement Tradeoffs for 400G Transmitter Designs
Understand the difference between leveraging Real time scopes and/or Equivalent time sampling scopes platforms and when to use each for Ultra high speed digital designs.
Enhancing Data Throughput – Every. Little. Thing. Matters.
Equalization, de-embedding and forward error correction all allow design engineers to push more data through a limited channel. This paper walks through the various techniques to make understanding them simple.
Data Center and Optical Network Ecosystem to Enable 5G
Deep dive with Thought leaders and experts from industry and discuss wireline innovations in this session.
Senior Director, Product Marketing
Synopsys DesignWare® HPC IP Solutions
Strategic Planner, USB Type-C® Ecosystem Solutions
Hadrien Louchet, Ph.D.
Application Development Engineer / Scientist
Strategic Product Planner
Dr. Joachim Peerlings
Vice President and General Manager
Power Integrity Lead