High-speed digital standards are rapidly changing to next generations to enable emerging technologies such as 5G, Internet of Things (IoT), artificial intelligence (AI), machine learning (ML), virtual reality (VR), and autonomous vehicles.

Each generational change introduces new test challenges for your digital designs. You need to test your high-speed digital designs across the entire product development lifecycle — including design and simulation, deployment, validation and debug, and manufacturing.

Join Keysight, DesignCon 2020 Host Sponsor, at our Booth 725 to discuss how we can help you anticipate test challenges, optimize performance, and accelerate your time-to-market. Be sure to stop by our booth to register to win a Lego Millennium Falcon. On Wednesday, January 29th, visit the Chiphead Theatre from 2:15 to 3:00 p.m. for the Leading Edge + Mainstream Technologies – Everything is Moving to Next Generation technical session.

January 28 – 30

Santa Clara Convention Center
Santa Clara, CA

Interactive Floor Plan and Exhibitor List

Program Details

Keysight’s technical experts and application engineers will demonstrate the most advanced design and test solutions, developed for solving today’s most difficult high-speed digital measurement challenges.

Keysight is proud to be the host sponsor of DesignCon 2020.


Great America 1 Conference Room

We are pleased to offer you all 8 Keysight Education Forum (KEF) sessions free of charge. Keysight’s test and measurement experts continue with KEF 2020 to showcase undeniable leadership and commitment across the high-speed digital and semiconductor markets.

Wednesday, January 29th Sessions

8:30 a.m. – 9:10 a.m.
DDR5/LPDDR5 Design, Debug, Probing, and Validation Challenges and Solutions

9:20 a.m. – 10:05 a.m.
Signal Integrity Simulation and Measurement Correlation: Getting Smart with Beatty Standard

10:15 a.m. – 10:55 a.m.
Be Prepared to Test Next-gen Type-C Technologies – eUSB2, USB 3.2, and USB4

11:05 a.m. – 11:45 a.m.
PCI Express Rockets Forward to 64GT/s: Phy Layer Testing Challenges at 32G NRZ and 64G PAM4

Thursday, January 30th Sessions

8:30 a.m. – 9:10 a.m.
5G is here, what does that mean for your high-speed digital work?

9:20 a.m. – 10:05 a.m.
Updates on the Challenges of Characterizing 112 Gbps/lane Designs

10:15 a.m. – 10:55 a.m.
Practical Bit Error Rate and RS(544,514) FEC Testing and Troubleshooting for PAM4 Links

11:05 a.m. – 11:45 a.m.
What You Need to Know Before Simulating DDR5 Memory Designs

Have questions or need help?