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October 8, 2020 (all times are India Standard Time)

10:00 AM – Data Center and Optical Network Ecosystem to Enable 5G
Deep dive with Thought leaders and experts from industry and discuss wireline innovations in this session.

10:30 AM – Data Center Technologies Move Toward $1 Per Gigabit
Understand how next-generation data center technologies help the industry to drastically reduce the cost of data center interconnects.

11:00 AM – Test & Measurement Trade-offs for 400G Transmitter designs
Understand the difference between leveraging Real time scopes and/or Equivalent time sampling scopes platforms and when to use each for Ultra-high-speed digital designs.

11:30 AM – Demo Break

11:45 AM – Enhancing Data Throughput – Every. Little. Thing. Matters
Equalization, de-embedding and forward error correction all allow design engineers to push more data through a limited channel. This paper walks through the various techniques to make understanding them simple.

12:15 PM – Understanding Compute Express Link technology for PCIe Gen5
In this session, we will be deep diving into next-generation CXL technology for PCIe Gen 5 and beyond.

12:45 PM – Demo Break

01:00 PM – Understanding Validation of DDR5/LPDDR5 and GDDR6 designs in 45 minutes
Faster networking speeds require faster memory. DDR5 and LPDDR5 effectively double the data rates of devices and server infrastructure with speeds 6.0 GT/s or higher. GDDR6 achieves never before speeds in graphics memory. This paper discusses solutions to the characterization of DDR5, LPDDR5, and GDDR6. Newly introduced Receiver testing for DDR5 is also discussed. Protocol and functional validation of DDR5/LPDDR5/GDDR6 are covered while discovering the techniques you’ll need to know to master a whole new generation of DRAM technologies.

01:45 PM – Improve Device Power Performance by Power Integrity Testing
Understand common Power Integrity and PMIC design issues. Improve test accuracy and efficiency by adopting the latest Power Integrity techniques.