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Key Features & Specifications

  • Versatile – tailored solutions for both the computer and server application spaces
  • Proven – M8000 BERT Series has been an effective tool for both compliance workshop testing and pathfinding
  • Accurate – vast experience in test automation combined with great instruments
  • Integration – built-in pattern generator de-emphasis, reference clock multiplier and error detectors equipped with clock recovery and equalization

Description

Combine Keysight’s M8000 Series BERT Systems with the unmatched performance of Keysight’s real-time oscilloscopes and the powerful N5990A / N5991PB5A Receiver Test Automation software to get the most versatile and complete receiver and LinkEQ test solution for PCI Express.

Versatile – tailored solutions for two different application spaces

Keysight offers two different receiver test solutions for PCI Express (the J-BERT M8020A based solution and the M8040A High-Performance BERT based solution). The J-BERT M8020A based solution is a perfect fit for receiver test needs for the computer application space. It covers PCI Express transfer rates ranging from 2.5 GT/s up to 16 GT/s. This system has become the “go to” receiver test solution for many of today’s computer standards in the same speed class including USB 3.0 / 3.1, SATA, SAS-3, MIPI M-PHY and DP sink testing.

PCI Express 4.0 Base Specification Receiver Test Setup based on J-BERT M8020A

See Recommended Configuration for Keysight J-BERT M8020A based PCI Express Receiver Test Setup.

The M8040A High-Performance BERT system is ideal for data center application space with its many different high-speed links inside and between servers. It supports baud rates up to 64 GBaud and encodes both NRZ and PAM4 signaling, making it the center piece of Keysight’s receiver test solutions for data center technologies. This solution targets PCI Express receiver testing for transfer rates of 32 GT/s as well as 16 GT/s and 8 GT/s. The M8040A based solution remains a great fit for 100G and 400G technologies.

PCI Express 5.0 Base Specification Receiver Test Setup based on M8040A High-Performance BERT

See Recommended Configuration for Keysight M8040A based PCI Express Receiver Test Setup.

Proven – M8000 BERT Series has been and continues to be an effective tool at compliance workshop testing and pathfinding

For years Keysight’s J-BERT M8020A based PCI Express Receiver and LinkEQ test solution has been used in Gold Suites at the official PCI Express compliance workshops to test Add-In cards and systems for 8G. Keysight and its partner BitifEye work together with standardization and test groups to assist during pathfinding, RX stress signal calibration and FYI testing. This ensures Keysight’s solution is fully qualified for these important tasks. J-BERT M8020A systems were extensively used for PCI Express 4.0 stress signal calibration development and Keysight outfitted PCI Express 4.0 16G LinkEQ FYI test suites at the official PCI Express compliance workshops right from the beginning. Early measurements for PCI Express 5.0 pathfinding for RX testing have been done with the M8040A High-Performance BERT and Keysight’s Z-Series real-time oscilloscope. The test automation was developed alongside the pathfinding process to speed up data collection and to assist customers with early RX stress signal calibration and test needs.

PCI Express RX and Link EQ Test Report J-BERT M8020A

Results can be reported as Excel workbook or as HTML report. Optionally results can be collected in a database. 

Accurate – vast experience in test automation combined with great instruments

PCI Express 3.0 marked a turning point for the importance of receiver testing in PCI Express. To cope with the rather long channel with losses of up to 20 dB at 4 GHz and a transfer rate of 8 GT/s in a plug and play environment, adaption of receiver equalization and even tuning of transmitter equalization dependent on requests of the receiver were necessary. Because of this receiver testing became mandatory for PCI Express 3.0 compliance. The complexity of the receiver stress signal calibration increased significantly with the shift from the reference away from DUT connection to a reference inside an adapting reference receiver. This process was further tuned with PCI Express 4.0 and PCI Express 5.0. Keysight and BitifEye, Keysight’s partner for test automation for receiver and LinkEQ testing, have worked together since PCI Express 2.0, they have been continuously improving the test automation to specification changes and to experience gained through active participation in compliance workshop testing. This combined with top of the line oscilloscopes and BERT systems offering a high degree of integration ensure accurate receiver and LinkEQ test solutions for PCI Express.

Integration – built-in pattern generator de-emphasis, reference clock multiplier and error detectors equipped with clock recovery and equalization

Some BERTs use supplemental instruments to realize important functions like pattern generator de-emphasis and error detector clock recovery as well as error detector equalization. While this can work, users must pay attention to setting up those add-on units correctly and to performing appropriate calibrations which ensures that propagation delays are handled correctly and other effects like losses through additional cabling are minimized. Keysight’s M8000 BERT Series pattern generators offer built-in de-emphasis as well as reference clock multipliers and the error detectors can be equipped with built-in clock recovery and equalization helping to minimize complexity of the receiver and LinkEQ setups while maintaining great flexibility to cover a great range of other receiver applications.

Key Challenges of PCI Express 3.0, 4.0 and 5.0 Receiver Testing

Starting with PCI Express 3.0 the receiver stress signal calibration targets are defined as eye height and eye width after applying a reference receiver which adapts to the stress signal. Additionally, the concept of transmitter de-emphasis optimization needs to be considered too. Taking the measurements requires special tools to determine the eye height and eye width. For Base Specification calibrations SEASIM, it is the preferred method which simulates the stress signal and reference receiver using a step measurement through the setup to determine channel characteristics and impairment parameters. Stress signal calibrations according to the PCI Express Architecture PHY Test Specification on the other hand requires the use of the waveform post processing tool SIGTEST. In both cases multiple eye height and eye width measurements must be averaged to achieve usable results per impairment and launch amplitude, de-emphasis, and preshoot combination. This requires a lot of measurements and a significant amount of processing time.

The actual stress signal calibration procedure differs between 8 GT/s, 16 GT/s and 32 GT/s. For instance, PCI Express 3.0 8 GT/s uses random jitter and differential mode sinusoidal interference as the main adjustments to achieve target eye height and eye width while PCI Express 4.0 16 GT/s uses channel loss adjustment for a first eye height and eye width adjustment followed by a tuning process using differential mode sinusoidal interference, sinusoidal jitter and launch amplitude. PCI Express 5.0 32 GT/s modified the stress signal calibration compared to PCI Express 4.0 16 GT/s slightly.

The test procedure for 8 GT/s receiver as defined in PCI Express 3.0 Base specification consisted of stressed voltage tests for three different channel scenarios and one stressed jitter test. The PCI Express Architecture PHY Test Specification defines one combined test and starting with PCI Express 4.0 the Base specification uses one combined receiver test too.

A software automating the calibration and test process and a PC with quite some processing power is highly recommended.

PCI Express 5.0 32 GT/s Receiver Test Automation N5991PB5A

Key Challenges of PCI Express Link Equalization Testing

The most significant change from PCI Express 2.0 to 3.0 other than the bit rate increase is the requirement for dynamic link equalization. Link equalization is critical for PCI Express 8 GT/s, 16 GT/s and 32 GT/s because the increased rate and length of transmission paths required in server interconnects cause increased signal integrity challenges. Signal equalizers are used at one or more locations in the link to compensate for signal anomalies by boosting the high-frequency components. Link equalization testing verifies the optimization of the link between a transmitter and receiver. The test solution acts as a link partner, and quickly negotiates transmitter to receiver communications using protocol handshakes.

Receiver link equalization testing exposes the device under test to stress signals similar to the standard receiver tests. But the device under test uses a protocol handshake process to fine tune the link’s performance by requesting changes of the BERT's data output de-emphasis and preshoot. The link is successfully trained once the receiver achieves the required bit error rate. This is checked with the bit error ratio in a loopback.
Transmitter equalization testing verifies that the device under test responds correctly to requests from the test equipment. The device under test's signal is analyzed by post processing waveforms captured on an oscilloscope. Response times of a device under test are verified by capturing the handshake between the BERT and the device under test.

PCI Express RX Test optional switch matrix

PCI Express RX Test Station Configuration including switch configuration for multi-lane testing

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PCI-SIG, PCI Express and PCIe are registered trademarks of PCI-SIG

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