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PathWave Advanced Design System (ADS) 2021 Product Release

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Key Features & Specifications

PathWave Advanced Design System (ADS) 2021 delivers includes:

  • General Design & Technology Management as well as Data Display improvements
  • Layout Design Editing improvements for routing, SmartMount, Ground Plans and more
  • Layout vs Layout Verification & ADS, Assura and Calibre DRC & Calibre LVS link enh
  • Faster Electro-Thermal/Circuit Envelope Simulation
  • RFPro EM Simulation Process Variation analysis and Momentum/FEM Gen 2 enhancements
  • RF/µW Circuit Simulation: Distortion EVM, Fast Circuit Envelope, 5G VTBs new capabilities
  • Design Kits: Enhanced Si-RFIC PDK Model Include Utility
  • High Speed Digital Improvements for SerDes, DDR/Memory, Signal and Power Integrity
  • Power Electronics enhancements: Model Builder, PEPro enhancements and more
  • And much more!

Learn about some of these new features and capabilites in the What's New in ADS 2021  video playlist on YouTube.

PathWave Advanced Design System (ADS) 2021 is available now!

Click the Trials & Licenses tab above, then click the Details & Download button to download the latest software.

Description

PathWave Advanced Design System (ADS)PathWave Advanced Design System (ADS) 2021 delivers solutions and more for challenging High-Speed Digital, RF & Microwave and Power Electronics designs including the following.

Design and Technology Management

General

  • Improved workspace performance when many libraries on a network path are included.
  • Enhanced Copy Cells command to handle references of Data Display files, to copy a cell from another workspace and provide a utility for finding and fixing missing references.
  • Enables the third-party version control systems to support tagging.
  • Supports "Patch" components.

Data Display

  • DDS equations management made easy:
    • Equation’s dependency information can be viewed via the Find > Show Hierarchy command.
    • The textual-based spreadsheet-like contents management system, the Expression Manager, provides a complementary method to the traditional graphics system for adding, viewing and editing equations and traces from all pages. The Expression Manager is dock-able to a DDS window and interoperates with the graphics system.
    • Facilitate the conversion of a DDS equation to an AEL function via the Command Line dialog box invoked from the Expression Manager.
      Ability to bulk editing of DDS plots and traces—for example, inserting, editing, replicating traces for multiple plots, changing trace attributes or plot attributes.
  • A new tool, Command Line, similar to ADS design environment’s AEL Command Line dialog box, enables exploring, editing and saving AEL functions intended for DDS equations.
  • Ability to import a DDS AEL file, and defines the AEL file loading frequency and timing, via the File > Import > AEL File menu. The loading of AEL file can be triggered at the workspace open, library open or ADS startup, respectively

Design Editing

  • Enhanced Layout Constraints Manager:
    • Ability to enable, disable or set a priority for a rule.
    • Teardrop, in addition to Via and Clearance, rules can be specified.
    • AEL APIs are available to enable scripting the rules.
  • Enhanced Ground Plane:
    • Ability to 'Lock' placement of a ground plane.
    • Ability to preserve the ground plane net during copy/paste.
  • Enhanced Keepout:
    • Ability to create a circular Keepout.
    • Ability to create a Keepout from an existing polygon, and vice versa.
    • Ability to edit a Keepout with visual cues of edge and vertex handles, similar to polygon editing.
    • Ability to include/exclude Keepout objects in selection operation.
  • Enhanced Routing:
    • Teardrops, a special connection pattern that optimizes the trace-to-pad, trace-to-via connection for improving the manufacturability of the layout, are inserted based on the rules that define the layers, height, offset, angle attributes.
    • Improved snapping, joining other interconnect, redundant segment removal, and back-tracking vertex during trace editing.
  • Enhaced Multi-technology Smart Mount:
    • Multi-Mount type, in addition to Bottom Mount and Flip Chip mount types, is added to support run-time decision on the mount type for the chip.
    • Ability to defined Chip to Module alignment for a Smart Mount Pcell via the File > Customize Pcell dialog box
  • General Editing Improvements:
    • Context-sensitive menus in Layout window and Navigator docking window are re-organized to make object-specific editing handy.
    • Instance position can be conveniently edited in the Properties docking window.
    • Instance’s OpenAccess Orientation is displayed in the Info docking window.
    • AEL APIs are available to enable padstack creation/editing and general layout object editing.

EM Simulation

RFPro

  • Analyze the impact of etch bias (over/under etch) and registration bias (layer misalignment) without the need for parameterizing the layout.
  • Simulation Service supporting cross-platform simulations. A Windows/Linux client can submit a simulation to a Linux cluster.
  • ADS now offers the possibility to place an encrypted EMPro 3D component inside the layout. Such a component can be seamlessly simulated inside RFPro ensuring the protection of the IP.
  • FEM Generation 2.
    • Now supports the simulation of a design with an encrypted substrate or containing an encrypted 3D component.
  • Usability
    • New Create Reference Pin On Layer option to serve as an implicit reference in the I/O or Component Model port definition.
    • New Create Delta Gap Port option to easily probe current in a design or tune a design.
    • Enhanced Component Model port editor facilitates the component port setup
    • Easy overlay of S-Parameters/TDR Results coming from different analyses.

Circuit Simulation

Stability analysis

  • Support for multiple--transistor stability analysis based on Ohtomo’s loop gain is added.
  • Improved efficiency of the stability post-processing functions

Design with Modulated Signals

  • Virtual testbenches (VTB)
    • Smoother flow to embed SystemVue Virtual Test Benches (VTB) inside ADS enabling updates without needing a new ADS version.
    • Regular Envelope can now be parallelized on multiple machines leading to huge speed-ups
  • Distortion EVM:
    • Streamlined the flow for an easier setup for designers.
  • Improvements of Fast Envelope for highly non-linear circuits (Fast Envelope Level5)

ElectroThermal

  • ETH Envelope sim speedup
  • Thermal viewer corrected power values shown in power source query
  • Checks the number of "independent" power sources in
  • ETH against licensing limits (ADS 2020 Update 2.0)
  • Fixed the reuse model extraction while using encrypted thermal technology (ADS 2020 Update 2.0)
  • Transient and CE Electrothermal sims now exit within a minute of an abort
  • ETH uses distinct run-dirs in Windows for each run (ADS 2020 Update 2.0)
  • Multiple encrypted techfiles in ETH (ADS2020 Update 1.0)
  • FloorPlanner results are now correctly handle power specified is in [mW/µW/pW] (ADS2020 Update1.0)

Design Kits

Si-RFIC PDK Model Include Utility

  • New configuration functions introduced
  • Setting hierarchy policy from the utility itself
  • Scalable dialog-box
  • Rename a scenario
  • Setting global model variables based on the global section

High-Speed Digital Design

DDR/SerDes

  • New IBIS Model Editor for pin-based model setting and batch simulation
  • New batch simulation setup for corner cases, model selector, etc
  • New Statistical Simulation mode for DDR5 AMI
  • New non-IBIS flow support
  • New pre-layout solution - DDR_PreLayout component
  • Memory Designer now supports bus transmission lines
  • Memory Designer supports HSPICE netlist for DDR_PreLayout component
  • Improved parser for IBIS models and PCB data files
  • New Design Exploration solution for pass/fail report generation
  • New TDECQ measurement with FlexDCA_Probe
  • New Infiniium_Probe, that sends ADS simulated waveforms to Infiniium offline software

PIPro

  • DC IR Drop allows for asymmetric voltage tolerances.
  • DC IR Drop results Power Tree expansion improved for parallel and cascaded VRMs.
  • AC Analysis auto loads sink excitation for field plots.
  • Fast update of PDN plots for enable/disable of components.
  • AC Analysis improved handling of schematic defined library models, multipin touchstone models, and embedded components. DeCap optimization works with library models, and results Loop Inductance works with embedded components.
  • Generate Analysis script now includes user defined virtual pins.

Power Electronics

Model from datasheet

  • Use IV, CV, and body diode measurements from a manufacturer’s datasheet to extract optimal parameters (“model card”) for a new ADS model that is suitable for Si and SiC power MOSFETs.

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