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Key Features & Specifications

Advanced Design System (ADS) 2019 Update 1.0 delivers new features and capabilities for:

Signal Integrity and Power Integrity Design

  • DDR5 Memory Designer
  • SIPro
  • PIPro
  • SerDes

Power Electronics Design

  • Expanded Library
  • Automated Simulation Setup
  • Automated Frequency Plan for Layout Parasitic Extraction

RF & Microwave Design

  • RFPro: Multi-technology/RF Module Simulation
  • 5G VTB Updated with Latest 5G NR Tests
  • Improved workspace management tools
  • Stackable PCB VIAs

ADS 2019 Update 1.0 is available for download now.

Click the Trials & Licenses tab above, then click the Details & Download button to download the latest software.

Description

Advanced Design SystemADS 2019 Update 1.0 is the next major step in delivering new capabilities, new technologies and more improvements to further improve design productivity and efficiency.

Signal Integrity and Power Integrity Design

ADS 2019 Update 1.0 delivers new features and capabilities for Signal Integrity and Power Integrity design.

DDR5 Memory Designer

Introducing a Revolutionized Workflow for Memory System Design. This new feature reduces DDR setup time from hours to minutes, and provides a predictive design flow for DDR4 and beyond.

  • New super-components for setup of memory controllers and memory devices - applying IBIS models as a group of signals.
  • 1-click connection of bus-wires between new super-components and PCB; connections are made automatically by matching Signal ID information.
  • 1 schematic for both Transient and DDR Bus sim, with no changes needed to be made to the schematic to swap between them. (The change of signal stimulus is changed and netlisted automatically).
  • New universal Memory Probe - provides intelligent access to signals anywhere within the schematic, and apply measurements as group.
  • Memory Probe can invoke automated DDR4 Compliance Testing - using Keysight's industry-proven measurement science (DDR4 Compliance test suite with the Infiniium, as used in hardware compliance test).

Memory Designer in PathWave ADS 2019 Update 1.0

Figure 1. Memory Designer in ADS 2019 Update 1.0.

SIPro Updates

  • Updates to SIPro to support Memory Designer Workflow, including a new DDR Setup wizard, to help generate EM setups in a highly productive manner - and a DDR Attribute editor, to view/edit the Signal IDs parsed from the layout information.
  • Huge speed up to SIPro Power-Aware SI EM extractions where power plane metallization and decaps are included in the extraction.

High-Speed Serial Channel Simulation

  • FlexDCA probe supports both Waveform Memory and Slot configurations, now enabling customers to easily transfer waveforms across to Keysight's FlexDCA, in order to access complex analyses like PAM-4 measurements including TDECQ, Jitter decomposition, and 802.3bs compliance tests and more).
  • New MIPI C-PHY 3-wire Tx and EyeProbe added to Channel Sim part palette. These new models work in both Channel Sim and Transient simulations, and allow the user to look at triggered and non-triggered eyes.
  • Channel Operating Margin (COM) is a channel compliance test used in IEEE 802.3bs and some JEDEC standards. This measurement similar to an SNR calculation, is now built-in as a new simulation option to the Channel Simulator. Supporting both IBIS-AMI and COM flow in a smooth workflow. This simulation option automatically invokes a Matlab Runtime (or optionally full version) in order to process the COM calculations as per the standard.
  • Back Channel Interface (BCI) - IBIS-AMI v7 models can provide support for link training; Whereby the Tx and Rx IBIS-AMI components that support the same BCI protocol, can pass messages to each other in order to optimize the Equalization settings in both Tx and Rx. For a user this is a huge usability and productivity improvement, and typically means that an optimum equalized eye can be achieved without needing to sweep every possible EQ setting in both models.

Signal Integrity/Power Integrity

  • Typically 70% reduction in memory usage for PIPro DC Electro-Thermal, and 1.5x performance speedup.
  • Performance improvements in DDR SIPro simulations, with huge speedups (5x or better) for simulations where Power-Aware simulation (power plane metallization and decaps) are included in the extraction.
  • New DDR analyses setup tool, including attribute editor allowing to view and modify DDR Signal IDs (attributes such as Reference Designator, Signal Type and Signal Index). An analysis for DDR generated using the DDR setup tool is optimized for speed.
  • For SIPro simulations, and PIPro-AC simulations, components models have a new option: ("Updating model does not require new simulation").
  • Enabling this option allows modifying the component value or model after the simulation. This is the default for new PIPro simulation setups.
  • Disabling this option no longer allows the component value to be changed except by performing a new simulation. This is the default for new SIPro simulation setups. Disabling this option typically improves the SIPro simulation time and memory requirements.
  • Capability to define back drill vias in SIPro, per net edited in a table.
  • Control for resource control for all SIPro and PIPro analysis with the capability to specify the number of threads being used during the analysis simulation.
  • Capability to remote simulate on LSF/PBS/Subgrid cluster when SIPro or PIPro user interface is launched on a machine in the cluster.

Power Electronics Design

ADS 2019 Update 1.0 delivers a new Power Electronics  Exapanded Library for Power Electronics design.

Power Electronics Library

  • Power Electronics specific controllers for Transient simulation, Harmonic Balance simulation and Simulation Options have been added to the Power Electronics library.
  • Schmitt components compatible with LTspice have been added to the Power Electronics library.
  • Set Dominant and Reset Dominant flip-flops have been added to the Power Electronics library.
  • Spectre compatibility has been added for Advanced Spice Model for High Electron Mobility Transistors (ASM-HEMT).

Automated Simulation Setup

Automated Frequency Plan for Layout Parasitic Extraction

RF & Microwave Design

ADS 2019 Update 1.0 delivers solutions and more for challenging RF & Microwave design including:

Circuit Simulation

Virtual Test Benches

  • The Virtual Test Benches have been upgraded to support the latest 5GNR tests.
  • Circuit data are now saved by default when using VTB to enable circuit insights under modulated signals conditions.

Support for new or updated models:

  • Support for the latest BSIM-IMG model (102.9.2)

EM Simulation

RFPro

  • New EM analysis capability for multi-technology designs (Nested Technology or Smart Mount):
    • Extracts physical interconnects crossing technology boundaries including bond wires.
    • Ports can be easily defined from (virtual) pins placed anywhere in the design hierarchy.
  • New User-Defined EM Extraction analysis type allows to EM-simulate selected nets of a large design.
  • The Dielectric Size Options context menu on a design provides control over the size of infinite dielectric layers for FEM simulations.
  • The Far Zone Sensor settings under the analysis Options → Frequency Plans → Fields Storage allows enabling or disabling far field computations. The angular resolution of the 3D far zone sensor can be specified as well.

EM Setup

  • A new 'SMPS' frequency plan type supports Switched Mode Power Supply simulations.

FEM

  • New control over the port calibration approach with the 'Direct', 'SMD' and 'Delta-Gap' Feed Type. For more information, see Ports in FEM.

Momentum

  • The Momentum layout preprocessing for FEM simulations has been enhanced to preserve the Feed Type in support of the new FEM port calibration capabilities.

Verification Test Bench (VTB)

  • The Single Port VTB (only Source) simulation is now supported. Now, you can create complex modulated sources in SystemVue and use with ADS Circuit Envelope.

Design and Technology Management

  • The new technology wizard has been updated to support adding a library/pdk technology not currently in the workspace.
  • Improved the performance of the reference DB and its impact on other operations.
  • Fixed the reference DB to handle read-only user libraries.
  • References and dependents window now prompts appropriate message if you delete something after listing its references or dependents.
  • Closing a modified design without saving now updates the reference db.
  • Removing a library or library definition file will warn you about dependents that are in the set of libraries being removed.
  • Check workspace now checks the problems in read-only user libraries when setting is enabled.

Design Editing

  • New Pcb vias are different in ADS 2019 Update 1.0. Old Pcb Vias are now called as ‘Padstack Templates’. You can create new Pcb Vias by specifying which padstack template to use and additionally user can specify start/stop layer and stackable attribute. For more information on New Pcb Vias, see Define and Insert PCB Vias and Pads using Padstack Templates.
  • A new Smart Mount subtype Multi-Mount is added. These are intended for designs that can be either used as a bottom mount, flip chip or a custom mount. The decision is left up to the module designer, at the time of instantiation of the smart mount design. The mounting type of this instance can also be changed once placed. For more information, see Multi-Mount under What is Smart Mount help topic.

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