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Prices for: United States

* Prices are subject to change without notice. Prices shown are Manufacturer's Suggested Retail Prices (MSRP). Prices shown are exclusive of taxes.

Key Features & Specifications

Product Highlights

  • The Interconnect Toolbox Element will design the stack up and line geometry of signal traces
  • Optimize the metrics that matter: Post-equalizer eye diagram parameters in a chip-to-chip link
  • Determine the constraints for the auto-router in your enterprise PCB or package tool
  • Via Designer will design parameterized single-ended and differential via geometries on your stackup
  • The via design is simulated with fullwave 3DEM simulation engine to produce a high-frequency accurate model.
  • Optimize the full link with parameterized via models and parameterized line models together for best eye metrics.


The W2307EP Interconnect Toolbox Element contains two utilities for the design of high-speed interconnects (transmission lines and via transitions respectively).

Interconnect Toolbox Utility

The Interconnect Toolbox utility enables you to optimize your PC board (PCB) stack up and transmission line geometry using metrics that matter, namely post-equalizer eye diagram parameters. Other tools will show you the impairments of the lines, such as loss, frequency roll off, and impedance variation, but in today's multi gigabit chip-to-chip links these metrics are inadequate. What really matters is the eye parameters after the line impairments have been mitigated by the signal processing in modern Serializer/Deserializer (SerDes), for example transmitter (Tx) pre-emphasis and reciever (Rx) equalization. In fact the whole point of the signal processing in the I/O of modern chips is to allow you to use lower cost materials and yet still open the eye.

CILD End-to-End Schematic

Figure 1. Combining the line type with a statistical eye Channel Simulation enables you use metrics that matter -- such as post-equaliztion eye opening height and width -- to optimize your controlled impedance lines.

The Interconnect Toolbox achieves this by letting you place a Tx and Rx around the candidate line to form a complete ADS Channel Simulator or ADS Transient Simulator schematic. In particular, the statistical mode of Channel Simulator can yield ultra low BER contours in seconds per point in the design space. You can quickly sweep parameters such as width and spacing to see the effect.

Controlled Impedance Line Designer Data Display Eye Diagrams

Figure 2. Pre- and post- equalization eye diagram sweep across line width. Pre- and post-equalization are the top and bottom rows, respectively. 1 mil width is on the left, 5 mil in the center, and 9 mil is on the right.

Via Designer Utility

The Via Designer Utility enables the user to quickly design both single-ended and differential via transitions.The via model can be fully parameterized and is analyzed with highly accurate 3D full-wave, Finite Element Method (FEM) simulation technology. The simulation results can be viewed within the utility (mixed-mode S-parameters), and the parameterized model can be exported for use in channel simulation. The extracted model contains a compact database of parameterized results allowing for efficient interpolation between simulated data.    

Via Designer

Figure 3. Via Designer graphical user interface.

With parameterized transmission lines, together with parameterized via transitions, the high-speed channel designer can co-optimize for metrics that matter (eye height and eye width).

Channel with Parameterized Vias

Figure 4. Channel simulation using parameterized vias from Via Designer.

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