Here’s the page we think you wanted. See search results instead:


Sprechen Sie mit einem Experten


Prices for: Deutschland

* Preisänderungen vorbehalten. Gerne können Sie Preise oder ein Angebot auch telefonisch anfragen bzw. anfordern unter 0800 6270999.

Key Features & Specifications

  • Adds PAM4 eye diagram analysis to the base NRZ default eye diagram analysis
  • Automatically measures PAM4 hitter, eye height, eye opening, eye width, etc
  • The base product N19301B is required to use this product


PLTS N19306B extends the N19301B base product to add PAM4 eye diagram analysis to the base product. The description below describes a fully configured PLTS system with latest features highlighted.

NEW PLTS 2020 64-bit application capability

The new Physical Layer Test System (PLTS) 2020 is the industry standard for signal integrity measurements and data post processing of high-speed interconnects, such as cables, backplanes, PCBs and connectors. Many signal integrity laboratories around the world have benefited from the power of PLTS in the R&D prototype test phase. PLTS 2020 has now migrated to a powerful 64-bit application unleashing high port count s-parameter measurements. Today’s internet infrastructure demands multi-port channel analysis to mitigate crosstalk issues that can cause bit errors. The new 64-bit PLTS application enables deeper memory for those large data files of 16-port and 32-port s-parameter measurements.

PAM4 Eye Diagram DFE Automatic Tap Optimization

Another significant enhancement to PLTS 2020 is the addition of Distributed Feedback Equalization (DFE) Automatic Taps within the Multi-Channel Simulator. This allows PAM4 eye diagram with a simple user interface to automatically select taps that open the eye at the receiver most efficiently. While a DFE filter uses a decision circuit as part of its feedback loop, selecting the proper poles and zeros to give best results can be hit or miss. With automatic tap selection in PLTS, the best eye is achieved quickly, thus
saving time for channel design.

Automatic Fixture Removal (AFR) Algorithm Enhancements

Automatic Fixture Removal is the industry standard for de-embedding test fixtures from channel measurements to obtain accurate s-parameters of only your device without performance degradation of the fixture taken into account. The problem in some applications can be that many laboratories around the world have inherited imperfect test fixtures that are not well designed. These marginal test fixtures can include such undesirable effects as differential skew, reflections, and ground plane discontinuities that can easily manifest crosstalk and mode conversion. Some test fixtures have large impedance discontinuities that can wreak havoc with de-embedding algorithms, but AFR has been further optimized to allow accurate propagation delay measurements of fixtures regardless of these test fixture design problems. Overall, a more robust de-embedding with added precision is the result.

New Standard Implemented: JCOM

Channel Operating Margin (COM) is an existing figure of merit that high speed digital designers are now using to create design trade-offs between active and passive channel components. It has proven to be flexible and efficient, albeit somewhat challenging to implement in the signal integrity laboratory. PLTS 2020 has already enhanced usability by running COM MATLAB dynamic link libraries within a user-friendly shell, so now COM is becoming more strongly embraced by the engineering community and standardization committee bodies such as OIF-CEI, Fibre Channel, and JEDEC as it continues to evolve. The newest emerging variation of the COM standard is called JCOM (JEDEC COM). JCOM addresses some COM limitations by allowing for custom device package and transceiver models to be used jointly with the COM algorithm. The new concept in JCOM relates to device variables such as rise/fall time filters, terminations, and packages. The computational algorithm is similar to the one from IEEE 802.3 COM, but the equalization optimization is performed for each possible combination of transmitter/receiver lanes and transmitter rise/fall times. JCOM is calculated as the minimum value resulting from all those combinations, and it is compared to a 2-dB threshold for channel compliance checking. As always, Keysight R&D engineers keep PLTS on the leading edge of technology by adopting the latest emerging standards to ensure product designs can be easily optimized for their highest performance.

Hardware Support

PLTS 2020 also supports the best-in-class family of high-performance PXI and USB Vector Network Analyzers. These flexible, scalable and re-configurable instruments allow for a smooth transition from R&D into manufacturing. They include the M980XA and P500XA series PNA family of VNA modules up to 20 GHz and can provide up to 50-port VNA measurements within a single test platform. This can potentially characterize 12 differential interconnect channels simultaneously with full cross-bar calibration with 140 dB of dynamic range with a single box. This level of high performance s-parameter characterization has never been available before now.

PNA Series Firmware, Upgrades, and Support

For more information about Keysight Network Analyzer, please visit Network Analyzer and Network Analyzer Software