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Keysight empowers innovators to break data speed records as they connect and secure the world. Whether you are pursuing 800G or 1.6T data speeds to accelerate the development of intelligent networks for artificial intelligence (AI) workloads, we empower you. Optimize your electrical and optical transmissions and data center interconnects with our leading design, emulation, and test solutions.
DATE
January 29 – 30, 2025
LOCATION
Santa Clara Convention Center
Santa Clara, California
KEYSIGHT BOOTH
1039
Discover Application Demonstrations
Visit us at Booth 1039, January 29 to 30, to see demos in action
Conference Papers by Keysight
Date |
Start time |
Session title |
Session type |
Room |
---|---|---|---|---|
January 28 | 9:00 a.m. |
Tutorial — Channel De-Embedding Methodology for Rx Stress Testing Using Fast-Edge Tx Waveform of BERT |
Tutorial |
Ballroom B |
January 28 | 9:00 a.m. |
Tutorial — Power Delivery Network Master Class on 2000A: How to Design, Simulate, and Validate |
Tutorial |
Ballroom A |
January 28 | 2:00 p.m. |
Tutorial — COM: A Field Guide for Serial Communication Link Designers |
Tutorial |
Ballroom D |
January 28 | 4:45 p.m. |
Panel — PCI Express and PAM4: Balancing Silicon and Interconnect Interdependencies for 128 GT/s |
Technical Panel |
Ballroom B |
January 29 | 11:15 a.m. |
Solving Common Problems with PCB Power Integrity Measurements and Simulations |
Chiphead Theater Session |
Chiphead Theater |
January 29 | 12:15 p.m. |
IBIS-AMI Modeling and Simulation of DMT in Preparation for 448 Gbps Applications |
Technical Paper Session |
Ballroom F |
January 29 | 4:00 p.m. |
Panel — Test on Wheels: Test and Measurement for Automotive Standards |
Technical Panel |
Ballroom H |
January 29 | 8:00 a.m. |
Practical Implementation of Insertion Loss Correction and Delay Characterization of Test Fixtures Used for 200 Gb/s Per Lane Conformance Testing |
Technical Paper Session |
Ballroom E |
January 29 | 2:00 p.m. |
Transmitter Power Spectral Density Noise Impact for 200 Gb/s PAM4 per Lane |
Technical Paper Session |
Ballroom C |
January 30 | 9:00 a.m. |
Innovative Design of 224G BGA Pin Map and Via Structure |
Technical Paper Session |
Ballroom D |
January 30 | 11:15 a.m. |
Modeling and Parameter Extraction of 224G PCB Under Variable Temperature and Research on the Influence of Temperature on Signal Integrity |
Technical Paper Session |
Ballroom B |
January 30 | 11:15 a.m. |
IBIS-AMI Modeling Formulation for Bidirectional MultiGBase-T1 Automotive Ethernet Links |
Technical Paper Session |
Ballroom C |
January 30 | 12:15 p.m. |
Beyond 200G: Brick Walls of 400G links per Lane |
Technical Paper Session |
Ballroom G |
January 30 | 12:45 p.m. |
LPDDR5 System-Level SI / PI Simulation for the Edge Artificial Intelligence System |
Chiphead Theater Session |
Chiphead Theater |
January 30 | 2:00 p.m. |
Accurate Adapter Removal in High-Precision, Low-Loss RF Interconnect Characterization |
Technical Paper Session |
Ballroom G |
January 30 | 3:00 p.m. |
It Takes a Village: 224Gb/s Mated Test Fixtures for Compliance |
Technical Paper Session |
Ballroom F |
January 30 | 4:00 p.m. |
Panel — Unbaking the Cake: The New Science of Compensating for Instrument Noise in Serial Data Measurements |
Technical Paper Session |
Ballroom C |
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