Join us for a virtual seminar with our Keysight PCIe 5.0, DDR5, Simulation experts, and others in your field. We’ll provide presentations, demos, and conversation (Q&A) with industry experts.

This seminar will cover test and validation methodologies, with best practice examples, to help PCIe 5.0 and DDR5 technology adopters fully test all key measurement parameters to ensure their design meets the specification requirements.

Learn the following:

  • Evolution of PCIe and DDR technologies
  • PHY Layer testing challenges at 32 GHz NRZ and 64 GT/s
  • Looking forward to PAM4 technologies
  • TX and RX test solutions for PCIe 5.0 and DDR5 Devices
  • Simulation and verification environments
  • New requirements for DDR5 simulation

AGENDA

  • 10:00 a.m. PT / 1:00 p.m. ET
    Leading Edge + Mainstream Technologies:  Everything is Moving to Next Generation
  • 10:30 a.m. PT / 1:30 p.m. ET
    Master PCIe Transmitter and Receiver Measurement Techniques
  • 11:45 a.m. PT / 2:45 p.m. ET
    Latest DDR5 Developments – Planning for DDR6

More info

DATE/TIME
May 6, 2020
10:00 a.m PT / 1:00 p.m. ET

DURATION
3 hours

LOCATION
Online
 
 
 

AGENDA

Leading Edge + Mainstream Technologies:  Everything is Moving to Next Generation

10:00 a.m. PT / 1:00 p.m. ET

The digital world is in the midst of some major changes, resulting in an exciting time for digital engineers. A few of the key trends we see are a fifth-generation revolution for PCIExpress© and DDR; a possibility of a convergence of DisplayPort, USB, and Thunderbolt; and PAM4 moving from communications into your typical high-speed digital standards. These changes come on top of the need for much higher speeds and lower power to handle the insatiable demand for more data from our consumers. As we see these trends beginning to impact our roadmaps, it is important to understand what it means to our testing buckets. Of course, Keysight would love for everyone to buy new test equipment, but the ramifications to this testing are more than simply purchasing new equipment. This presentation will discuss the key trends and what you should know as you look to test the latest technologies.

Master PCIe Transmitter and Receiver Measurement Techniques

10:30 a.m. PT / 1:30 p.m. ET

Key Learnings:

  • How artificial intelligence and solid-state storage technologies are driving the need for faster data transmission speeds in I/O interconnect technologies.
  • Key techniques to perform Tx and RX characterization along with additional measurement requirements to consider as PCIe adopts PAM4 signaling. 
  • What backward compatibility of PCIe 5.0 and 6.0 means for developers of PCIe 3- and PCIe 4-based systems and devices. 
 

Latest DDR5 Developments – Planning for DDR6

11:45 a.m. PT / 2:45 p.m. ET

Key learnings: 

  • What are the changes from DDR4 to DDR5, what comes after DDR5, and why new simulation and measurement techniques are necessary.
  • How to apply the new simulation technology within productive and predictive DDR5 workflow using PathWave ADS with Memory Designer
  • How to verify compliance; as well as, identify and troubleshoot problems in prototype and production systems employing the next generation of memory.

Keysight’s Experts

Rick Eads

Principal PCI Express Program Manager

Director, PCI-SIG Member, PCISIG Electrical Work Group (EWG), Card Electromechanical Work group (CEG), Serial Enabling Work Group (SEG)

Co-Chair: GenZ Compliance and Interoperability work group

Perry Keller

Digital Standards and Applications Program Lead

Memory Program Manager
JEDEC Board of Directors
Chairman, JC40.5, JC45.5, and JC64.5 Validation Committees

Stephen Slater

Product Planning and Marketing Manager for SI / PI Simulation Software

Keysight PathWave Software Solutions 
Member of SI Journal Editorial Advisory Board

Brig Asay

Strategic Planning Manager

Internet Infrastructure Group

Have questions or need help?