Advanced Topics in Signal Integrity and Power Integrity Seminar

Join Keysight to explore the latest in innovations in Signal Integrity and Power Integrity in ADS 2023. See how parallel simulations speed up circuit design. We will show you how PAM-3 is used in USB4 v2, and how to ensure you are generating casual S-Parameter models from your EM simulator. *Bring your laptop and your questions for our Specialists!

AGENDA

9:00 a.m. / Registration

9:30 a.m.
Memory: Advances in Memory System Design Workflow

• What's new in Memory Designer in the latest releases
• Advanced memory interface for pathfinding
• Latest simulation examples and demos

10:30 a.m.
Simulate with Confidence: Your Next Gen SerDes Design! We will be discussing some of the latest SerDes standards that enable hyerscale computing.

• PCIe 6 & 5
• CXL 2
• USB4V2 (and USB4 Gen2 & 3)

11:30 a.m. / Lunch

12:30 p.m.
EM Modeling: Successful Extraction of High-Speed PCB Designs in Less TIme

• How SIPro can help you successfully simulate your High-Speed PCB Designs
• Discussion on port setup, meshing and causality of extracted EM models
• Simulation workflow (Python script based) automation examples demonstrating increased productivity

1:30 p.m.
Expanding Power Integrity Simulations to Include Cascaded VRMs

• An iterative EM approach determines the average DC behavior, when dynamic regulators are cascaded in series
• Steady-state behavior for an AC EM PCB model with cascaded dynamic switching regulators is solved using Harmonic Balance
• Advanced conducted EMI simulations of cascaded VRM's help to analyze separate power rail noise vs. ground rail noise

2:30 p.m.
Optional ADS Clinic and Afternoon Tea
Bring your laptop and your questions for the specialists!

Date/Time
Wednesday, May 10, 2023
9:30 a.m. - 3:00 p.m.

Registration
9:00 a.m.

Location
Keysight Technologies
5301 Stevens Creek Blvd.
Santa Clara, CA 95051

Event Location: Agilent Main Lobby; Bldg 5