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PCIe® and Chiplet PHY Designers
Fewer prototypes and faster compliance with end-to-end simulation and standards-driven workflows.
Introducing standards-driven design workflows
With the increasing complexity of electronics, designers need enhanced automation and collaborative tools to comply with stringent standards. Introducing PCIe 5/6 and chiplet die-to-die design workflows with Keysight EDA:
- System Designer for PCIe® enables designers to perform complete PCIe® 5/6 system analysis and simulation-driven virtual compliance tests with a streamlined workflow.
- Chiplet PHY Designer enables designers to predict chiplet die-to-die link margin performance and measure voltage transfer function compliance for the Universal Chiplet Interconnect Express™(UCIe™) standard.
Standards compliance verification applications
PCIe 5/6 signal integrity, and virtual compliance test
The System Designer for PCIe® automates the setup for multi-link, multi-lane, and multi-level (PAM4) PCIe systems using a smart design environment.
The PCIe AMI modeler, which supports NRZ and PAM4 modulations, facilitates the quick implementation of PCIe systems. The integrated simulation-driven compliance test solution can reduce design costs by minimizing design iterations and shortening time-to-market.
Chiplet die-to-die link signal integrity, and compliance verification
The Chiplet PHY designer allows designers to predict the end-to-end link margin and compliance measures such as voltage transfer function (VTF) for chiplet’s die-to-die interconnects.
It allows the forwarded clocking in UCIe to be accurately analyzed to consider the jitter tracking. Built-in support for standard-specific measurements makes verifying compliance with known chiplet standards easy.
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