WEBVTT NOTE This file was exported by MacCaption version 7.0.13 to comply with the WebVTT specification dated March 27, 2017. 00:00:01.969 --> 00:00:06.373 align:center line:-1 position:50% size:53% In this next section, I'll be going through some of the things we've learned 00:00:06.373 --> 00:00:09.610 align:center line:-1 position:50% size:61% about receiver tests and some considerations 00:00:09.610 --> 00:00:13.947 align:center line:-1 position:50% size:37% for doing calibration for receiver tests for Gen 5. 00:00:13.947 --> 00:00:18.552 align:center line:-1 position:50% size:57% PCI Express® in the card electromechanical or CEM form factor 00:00:18.552 --> 00:00:24.758 align:center line:-1 position:50% size:58% is designed to support two different classes or types of channel topologies, 00:00:24.758 --> 00:00:28.028 align:center line:-1 position:50% size:53% one you can think of as a short channel or a client topology 00:00:28.028 --> 00:00:33.934 align:center line:-1 position:50% size:50% and the other one is a longer channel or a server type topology. 00:00:33.934 --> 00:00:38.405 align:center line:-1 position:50% size:51% Because of the speed and the amount of attenuation of these channels, 00:00:38.405 --> 00:00:48.048 align:center line:-1 position:50% size:66% overall, PCI Express is intended to accommodate a total diapad to diapad loss of about -36 dB, 00:00:48.048 --> 00:00:55.222 align:center line:-1 position:50% size:63% and when you get to longer channels that comprehend more than a single connector, 00:00:55.222 --> 00:00:59.259 align:center line:-1 position:50% size:47% it's likely that you'll need some type of channel extension technology 00:00:59.259 --> 00:01:03.797 align:center line:-1 position:50% size:52% and the specification supports a device referred to as a retimer, 00:01:03.797 --> 00:01:06.700 align:center line:-1 position:50% size:45% which gives you a full card electromechanical path 00:01:06.700 --> 00:01:11.838 align:center line:-1 position:50% size:43% on the upstream side as well as on the downstream side. 00:01:11.838 --> 00:01:17.511 align:center line:-1 position:50% size:64% Receiver testing for both Gen 4 and Gen 5 is probably one of the more challenging aspects 00:01:17.511 --> 00:01:20.247 align:center line:-1 position:50% size:47% of validating a PCI Express device, 00:01:20.247 --> 00:01:24.051 align:center line:-1 position:50% size:37% and while it isn't necessarily the receiver test itself 00:01:24.051 --> 00:01:25.752 align:center line:-1 position:50% size:35% that's the challenging part, 00:01:25.752 --> 00:01:29.957 align:center line:-1 position:50% size:48% I think the real challenge is creating the stressed conditions 00:01:29.957 --> 00:01:32.159 align:center line:-1 position:50% size:47% under which you'd test your device. 00:01:32.159 --> 00:01:37.864 align:center line:-1 position:50% size:63% When we're doing a stressed receiver test, for example, for Gen 5 or Gen 4 for that matter, 00:01:37.864 --> 00:01:41.568 align:center line:-1 position:50% size:56% we're trying to answer a specific question, and that question is, 00:01:41.568 --> 00:01:46.406 align:center line:-1 position:50% size:46% "when presented with a worst case yet valid PCI Express signal, 00:01:46.406 --> 00:01:51.378 align:center line:-1 position:50% size:46% is the receiver capable of applying the proper equalization necessary 00:01:51.378 --> 00:01:56.350 align:center line:-1 position:50% size:42% to achieve a bit error ratio of one error in 10 to the 12 bits." 00:01:56.350 --> 00:01:58.685 align:center line:-1 position:50% size:21% That's the goal. 00:01:58.685 --> 00:02:04.558 align:center line:-1 position:50% size:55% With PCI Express Gen 4, we adjusted from the Gen 3 test methods 00:02:04.558 --> 00:02:10.497 align:center line:-1 position:50% size:41% to start with a nominal cocktail of jitter components 00:02:10.497 --> 00:02:16.436 align:center line:-1 position:50% size:67% consisting of RJ, Sinusoidal jitter, differential mode, and common mode interference, 00:02:16.436 --> 00:02:23.877 align:center line:-1 position:50% size:54% and the vast majority of the impairments used to create this stressed eye signal 00:02:23.877 --> 00:02:30.017 align:center line:-1 position:50% size:64% are made by adding incremental amounts of ISI. 00:02:30.017 --> 00:02:36.323 align:center line:-1 position:50% size:50% The reason we do that is because ISI is likely to be the best reflection 00:02:36.323 --> 00:02:41.528 align:center line:-1 position:50% size:52% of the main impairment that that device is likely to see in the field 00:02:41.528 --> 00:02:46.233 align:center line:-1 position:50% size:47% and also the equalization schemes that are designed for PCI Express 00:02:46.233 --> 00:02:54.341 align:center line:-1 position:50% size:63% are intended to accommodate the linear effects that dominate the ISI channel. 00:02:54.341 --> 00:02:58.779 align:center line:-1 position:50% size:50% Also with Gen 4, we added the card electromechanical connector 00:02:58.779 --> 00:03:01.214 align:center line:-1 position:50% size:46% as part of that calibration channel, 00:03:01.214 --> 00:03:06.620 align:center line:-1 position:50% size:50% and we'll go into a little bit more detail on that a little bit later 00:03:06.620 --> 00:03:12.259 align:center line:-1 position:50% size:64% as far as what those physical channels look like and what's available from the PCI-SIG®, 00:03:12.259 --> 00:03:17.631 align:center line:-1 position:50% size:64% but the overall goal is to take those impairments and to construct AI 00:03:17.631 --> 00:03:24.738 align:center line:-1 position:50% size:56% that after equalization equates to about 15 mV of eye height and .3 UI of eye width, 00:03:24.738 --> 00:03:29.476 align:center line:-1 position:50% size:39% so that's a pretty tight margin for PCI Express Gen 5. 00:03:29.476 --> 00:03:34.181 align:center line:-1 position:50% size:41% PCI Express Gen 5 calibration for the bit error ratio tester 00:03:34.181 --> 00:03:38.685 align:center line:-1 position:50% size:41% was leveraged substantially off of the calibration process 00:03:38.685 --> 00:03:42.889 align:center line:-1 position:50% size:48% that was developed for PCI Express Gen 4 shown here. 00:03:42.889 --> 00:03:47.994 align:center line:-1 position:50% size:54% You have the same overall approach of where you have nominal jitter sources 00:03:47.994 --> 00:03:51.865 align:center line:-1 position:50% size:43% of RJ, SJ, differential, and common-mode interference 00:03:51.865 --> 00:03:56.269 align:center line:-1 position:50% size:41% as well as the nominal concept of using a variable ISI channel 00:03:56.269 --> 00:04:00.006 align:center line:-1 position:50% size:46% with an embedded card electromechanical connector, 00:04:00.006 --> 00:04:05.879 align:center line:-1 position:50% size:62% and overall, the PCI Express Gen 4 and Gen 5 eye height and eye width requirements 00:04:05.879 --> 00:04:13.687 align:center line:-1 position:50% size:62% for the stress receiver calibration are the same at 15 mV of eye height and .3 UI of eye width. 00:04:13.687 --> 00:04:16.690 align:center line:-1 position:50% size:38% There are a couple of subtle yet important differences 00:04:16.690 --> 00:04:21.161 align:center line:-1 position:50% size:40% when it comes to the stressed receiver-test calibration 00:04:21.161 --> 00:04:26.133 align:center line:-1 position:50% size:58% for PCI Express 4 and 5 that are noted in the slide and summarized, 00:04:26.133 --> 00:04:31.204 align:center line:-1 position:50% size:62% but a couple of things I wanted to point out is you have to pay attention to what's included 00:04:31.204 --> 00:04:35.842 align:center line:-1 position:50% size:50% and what's not included in the calibration channel for 4 and 5. 00:04:35.842 --> 00:04:42.082 align:center line:-1 position:50% size:61% In 4, for example, we include the BERT cable, which is not included in the Gen 5 calibration. 00:04:42.082 --> 00:04:46.820 align:center line:-1 position:50% size:53% Also, some differences exist in the steps for closing the calibration. 00:04:46.820 --> 00:04:50.457 align:center line:-1 position:50% size:45% Overall, the objective for Gen 4 is to find the highest channel loss 00:04:50.457 --> 00:04:55.996 align:center line:-1 position:50% size:57% where eye width and eye height meet minimum receiver test requirements, 00:04:55.996 --> 00:05:00.834 align:center line:-1 position:50% size:56% whereas for Gen 5, really you want to find the highest loss ISI channel pair 00:05:00.834 --> 00:05:05.205 align:center line:-1 position:50% size:47% where you can close the calibration while you're also sweeping SJ 00:05:05.205 --> 00:05:07.574 align:center line:-1 position:50% size:52% and DMSI through the allowed ranges. 00:05:07.574 --> 00:05:13.680 align:center line:-1 position:50% size:58% Those are the two main differences as to how we get to the closed calibrations. 00:05:13.680 --> 00:05:15.448 align:center line:-1 position:50% size:47% There are some assumptions here. 00:05:15.448 --> 00:05:18.985 align:center line:-1 position:50% size:43% SJ allowances and adjustments in those that are minor 00:05:18.985 --> 00:05:25.025 align:center line:-1 position:50% size:48% can be used to adjust eye width and DMSI allows adjustments there 00:05:25.025 --> 00:05:28.094 align:center line:-1 position:50% size:45% and can be used to adjust eye height. 00:05:28.094 --> 00:05:31.064 align:center line:-1 position:50% size:38% Here's the thing: In practice, what we have observed 00:05:31.064 --> 00:05:37.437 align:center line:-1 position:50% size:51% is that changes in SJ can also change both eye width and eye height. 00:05:37.437 --> 00:05:43.443 align:center line:-1 position:50% size:59% A changed DMSI also can result in changes to both eye width and eye height 00:05:43.443 --> 00:05:49.683 align:center line:-1 position:50% size:52% at 32 Gb/s, so even though those ideas were first conceived at 16 Gb, 00:05:49.683 --> 00:05:54.354 align:center line:-1 position:50% size:37% when it get to 32 Gb/s, things can get a lot touchier, 00:05:54.354 --> 00:05:58.325 align:center line:-1 position:50% size:45% and it can get much more difficult to close the calibration. 00:05:58.325 --> 00:06:04.164 align:center line:-1 position:50% size:62% This is why it's important, I think, to make sure that you're getting your test tools from-- 00:06:04.164 --> 00:06:06.700 align:center line:-1 position:50% size:44% I would recommend getting them from a single vendor, 00:06:06.700 --> 00:06:13.540 align:center line:-1 position:50% size:64% because then you have a very good mechanism for ensuring that the probability 00:06:13.540 --> 00:06:18.545 align:center line:-1 position:50% size:52% of you being able to close a calibration is the highest that it's going to be. 00:06:18.545 --> 00:06:20.614 align:center line:-1 position:50% size:39% These are challenging things, 00:06:20.614 --> 00:06:24.784 align:center line:-1 position:50% size:54% and we've gone through an extensive amount of work at Keysight 00:06:24.784 --> 00:06:27.754 align:center line:-1 position:50% size:39% starting manually developing a calibration process 00:06:27.754 --> 00:06:32.492 align:center line:-1 position:50% size:56% and then going through a process of formally automating that test procedure 00:06:32.492 --> 00:06:35.996 align:center line:-1 position:50% size:61% to be able to confidently close the calibrations 00:06:35.996 --> 00:06:40.333 align:center line:-1 position:50% size:47% with the channels that are provided for PCI Express testing. 00:06:40.333 --> 00:06:41.333 align:center line:-1 position:50% size:47% PCI-SIG® and PCI Express® are US registered trademarks and/or service marks of PCI-SIG.