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Most of our customers have a huge amount
of knowledge working on many different standards,

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and in all these standards,
there's a definition of a test point.

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For example, you see TP0,
TP1, TP2, TP3, TP4, TP3''.

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All these test points have to do
with where in the link the test point is.

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For example, TP0, TP1,
is very often right at the bond wires of silicon,

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perhaps TP2 is right at the Type-C connector,

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TP3'' is maybe inside the receiver
after equalization and clock recovery,

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but every standard has
a different definition of test points.

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There's no right or wrong,
so customers tend to get stuck.

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Sometimes they say,
"Hey, they changed the test point."

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There's no right or wrong definition.

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The key thing is to go to the USB4 spec
and read carefully the definition,

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not the picture of what it is.

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Two examples.

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When they moved from the Thunderbolt 3 test point
to USB4,

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they changed not the definition of the test points
but they renamed, for example, TP3 EQ to TP3.

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It's not right or wrong,
it's just a different name,

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but the spec is very clear about where it is.

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Understanding the definition of test point
for USB4 is critical,

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otherwise the testing will be done
at the wrong spot

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and the margins will be completely inaccurate.

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That's another huge gotcha.

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Just this week alone,
I probably have three emails from customers

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who are confused about the test point definition,
mainly because it's changed.

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Sometimes it's because it's not how
they understood it from a different technology,

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but the bottom line is,
you've got to look at a spec,

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and you've got to understand how USB4--

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not Thunderbolt 3, not USB 3.2, not PCI--

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it's how USB4 defines the test points.

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That's another gotcha that gets customers
into lots of issues.

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It sounds like the gotcha is,
someone sees TP3

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and they just assume they know
what that means for their spec,

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but because it's different from spec to spec
and even from 3.2 to 4.0, for example,

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people are getting confused or thrown off,
and they need to go back and read the spec.

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That's exactly correct.

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In fact, if you look at the USB4 spec,
and I'm looking at a picture over here,

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and if you see where they draw TP3
in the USB4 spec,

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it looks from the picture like TP4

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is where the test point that includes
the clock recovery and receiver equalization is.

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That's what it looks like in the diagram, but
if you look at the definition, that's not correct.

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Even the picture in the USB4 spec
could be confusing, but the wording is very clear.

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It says that TP3 is measured at the receptacle
side, and it applies the reference equalizer.

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Even within the same spec,
you have to not just look at the picture

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and assume, "Hey, TP4 is right where
the receiver equalization should be,"

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you need to read the words.

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That's where some of the confusion can come from

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if you're not being super rigorous
with some of these definitions.

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Okay, interesting.

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Is that spec public?

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Yes, it absolutely is.

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Thunderbolt 3 was and continues to be
an Intel proprietary spec,

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so most folks do not have access
to the Thunderbolt 3 spec,

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but the USB-IF is very different.

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If you just Google "USB.org"
or "USB-IF USB4 spec,"

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anybody in the world has full access
to the USB4 spec.

