!!!!    6    0    1  987185144  V1799                                         

! Device           : 16dp8
! Function         : Dual-Port RAM
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle   300n
receive delay  200n

!+++++++++++++ Power ++++++++++++++!
assign VCC to pins 68
assign GND to pins 18,36,52

!+++++++++++ No Connect +++++++++++!
assign NC          to pins 9,25,26,27,35,43,44

!+++++++ Address/Data Bus +++++++++!
assign Addrs_left     to pins 3,65,5,7,10,12,63,61,59,57
assign Data_left      to pins 51,48,45,40,33,30,24,21     !Can access 2 bytes.
assign Data_left      to pins 49,46,41,38,31,28,22,19
assign Data_left_D0   to pins 19   !AT Added for minimum pin test.
assign Data_left_D1   to pins 22   !AT Added for minimum pin test.
assign Data_left_D2   to pins 28   !AT Added for minimum pin test.
assign Data_left_D3   to pins 31   !AT Added for minimum pin test.
assign Data_left_D4   to pins 38   !AT Added for minimum pin test.
assign Data_left_D5   to pins 41   !AT Added for minimum pin test.
assign Data_left_D6   to pins 46   !AT Added for minimum pin test.
assign Data_left_D7   to pins 49   !AT Added for minimum pin test.
assign Data_left_D8   to pins 21   !AT Added for minimum pin test.
assign Data_left_D9   to pins 24   !AT Added for minimum pin test.
assign Data_left_D10  to pins 30   !AT Added for minimum pin test.
assign Data_left_D11  to pins 33   !AT Added for minimum pin test.
assign Data_left_D12  to pins 40   !AT Added for minimum pin test.
assign Data_left_D13  to pins 45   !AT Added for minimum pin test.
assign Data_left_D14  to pins 48   !AT Added for minimum pin test.
assign Data_left_D15  to pins 51   !AT Added for minimum pin test.

assign Addrs_right    to pins 66,4,64,62,60,58,6,8,11,13
assign Data_right     to pins 50,47,42,39,32,29,23,20     !Can access 1 byte.
assign Data_right_D0  to pins 20   !AT Added for minimum pin test.
assign Data_right_D1  to pins 23   !AT Added for minimum pin test.
assign Data_right_D2  to pins 29   !AT Added for minimum pin test.
assign Data_right_D3  to pins 32   !AT Added for minimum pin test.
assign Data_right_D4  to pins 39   !AT Added for minimum pin test.
assign Data_right_D5  to pins 42   !AT Added for minimum pin test.
assign Data_right_D6  to pins 47   !AT Added for minimum pin test.
assign Data_right_D7  to pins 50   !AT Added for minimum pin test.

!****************************** Control Lines ******************************!

!+++++++++++ Left Side +++++++++++!
assign CEL_bar     to pins 14          !Left port chip enable.
assign OEL_bar     to pins 16          !Left port output enable.
assign WEL_bar     to pins 17          !Left port write enable.
assign BusyL_bar   to pins 1           !Left port busy flag output.
assign INTL_bar    to pins 34          !Left port interrupt output.
assign BHE_bar     to pins 2           !Byte high enable.
assign BLE_bar     to pins 15          !Byte low enable.

!++++++++++ Right Side +++++++++++!
assign CER_bar     to pins 56          !Right port chip enable.
assign OER_bar     to pins 54          !Right port output enable.
assign WER_bar     to pins 53          !Right port write enable.
assign BusyR_bar   to pins 67          !Right port busy flag output.
assign INTR_bar    to pins 37          !Right port interrupt output.
assign Up_Low_bar  to pins 55          !Right port upper or lower byte select.

family TTL

power  VCC,GND

nondigital     NC

inputs  Addrs_left,CEL_bar,OEL_bar,WEL_bar,BHE_bar,BLE_bar
inputs  Addrs_right,CER_bar,OER_bar,WER_bar,Up_Low_bar

outputs BusyL_bar,INTL_bar,BusyR_bar,INTR_bar

bidirectional Data_left,Data_right

bidirectional Data_left_D0, Data_left_D1        !AT Added for min. pin test.
bidirectional Data_left_D2, Data_left_D3        !AT Added for min. pin test.
bidirectional Data_left_D4, Data_left_D5        !AT Added for min. pin test.
bidirectional Data_left_D6, Data_left_D7        !AT Added for min. pin test.
bidirectional Data_left_D8, Data_left_D9        !AT Added for min. pin test.
bidirectional Data_left_D10, Data_left_D11      !AT Added for min. pin test.
bidirectional Data_left_D12, Data_left_D13      !AT Added for min. pin test.
bidirectional Data_left_D14, Data_left_D15      !AT Added for min. pin test.

bidirectional Data_right_D0, Data_right_D1      !AT Added for min. pin test.
bidirectional Data_right_D2, Data_right_D3      !AT Added for min. pin test.
bidirectional Data_right_D4, Data_right_D5      !AT Added for min. pin test.
bidirectional Data_right_D6, Data_right_D7      !AT Added for min. pin test.

format hexadecimal Data_left,Data_right

!
!  Disable Information
!

disable  Data_left                    with OEL_bar  to "1"
disable  Data_right                   with OER_bar  to "1"


!
!  Trace information
!

when  WEL_bar     is "0"     inputs  Data_left
when  WEL_bar     is "1"     outputs Data_left
when  WER_bar     is "0"     inputs  Data_right
when  WER_bar     is "1"     outputs Data_right

when  OEL_bar     is "1"     inactive Data_left
when  OER_bar     is "1"     inactive Data_right


!*****************************************************************************!
!**********************Vector Definition Section******************************!
!*****************************************************************************!

vector Initial_Inputs
  set CEL_bar            to "1"
  set OEL_bar            to "1"
  set WEL_bar            to "1"
  set BHE_bar            to "1"
  set BLE_bar            to "1"
  set CER_bar            to "1"
  set OER_bar            to "1"
  set WER_bar            to "1"
  set Up_Low_bar         to "1"
end vector

vector Keep_Control
  set CEL_bar            to "k"
  set OEL_bar            to "k"
  set WEL_bar            to "k"
  set BHE_bar            to "k"
  set BLE_bar            to "k"
  set CER_bar            to "k"
  set OER_bar            to "k"
  set WER_bar            to "k"
  set Up_Low_bar         to "k"
end vector

vector Left_chip_disable
  initialize       to Keep_Control
  set CEL_bar      to "1"
end vector

vector Left_chip_enable
  initialize       to Keep_Control
  set CEL_bar      to "0"
end vector

vector Right_chip_disable
  initialize       to Keep_Control
  set CER_bar      to "1"
end vector

vector Right_chip_enable
  initialize       to Keep_Control
  set CER_bar      to "0"
end vector

vector Left_output_disable
  initialize       to Keep_Control
  set OEL_bar      to "1"
end vector

vector Left_output_enable
  initialize       to Keep_Control
  set OEL_bar      to "0"
end vector

vector Right_output_disable
  initialize       to Keep_Control
  set OER_bar      to "1"
end vector

vector Right_output_enable
  initialize       to Keep_Control
  set OER_bar      to "0"
end vector

vector Left_write_disable
  initialize       to Keep_Control
  set WEL_bar      to "1"
end vector

vector Left_write_enable
  initialize       to Keep_Control
  set WEL_bar      to "0"
end vector

vector Right_write_disable
  initialize       to Keep_Control
  set WER_bar      to "1"
end vector

vector Right_write_enable
  initialize       to Keep_Control
  set WER_bar      to "0"
end vector

vector BusyL_false
  initialize       to Keep_Control
  set BusyL_bar    to "1"
end vector

vector BusyL_true
  initialize       to Keep_Control
  set BusyL_bar    to "0"
end vector

vector BusyR_false
  initialize       to Keep_Control
  set BusyR_bar    to "1"
end vector

vector BusyR_true
  initialize       to Keep_Control
  set BusyR_bar    to "0"
end vector

vector INTL_false
  initialize       to Keep_Control
  set INTL_bar     to "1"
end vector

vector INTL_true
  initialize       to Keep_Control
  set INTL_bar     to "0"
end vector

vector INTR_false
  initialize       to Keep_Control
  set INTR_bar     to "1"
end vector

vector INTR_true
  initialize       to Keep_Control
  set INTR_bar     to "0"
end vector

vector Byte_high_disable
  initialize       to Keep_Control
  set BHE_bar      to "1"
end vector

vector Byte_high_enable
  initialize       to Keep_Control
  set BHE_bar      to "0"
end vector

vector Byte_low_disable
  initialize       to Keep_Control
  set BLE_bar      to "1"
end vector

vector Byte_low_enable
  initialize       to Keep_Control
  set BLE_bar      to "0"
end vector

vector Word_disable
  initialize       to Keep_Control
  set BHE_bar      to "1"
  set BLE_bar      to "1"
end vector

vector Word_enable
  initialize       to Keep_Control
  set BHE_bar      to "0"
  set BLE_bar      to "0"
end vector

vector Select_upper_byte
  initialize       to Keep_Control
  set Up_Low_bar   to "1"
end vector

vector Select_lower_byte
  initialize       to Keep_Control
  set Up_Low_bar   to "0"
end vector

vector Write_cycle_end_left
  initialize       to Keep_Control
  set CEL_bar      to "1"
  set WEL_bar      to "1"
end vector

vector Write_cycle_end_right
  initialize       to Keep_Control
  set CER_bar      to "1"
  set WER_bar      to "1"
end vector

!+++++++++++++++Address Vectors ++++++++++++++!

vector AddressL_1010101010
  initialize       to Keep_Control
  set Addrs_left   to "1010101010"
end vector

vector AddressL_0101010101
  initialize       to Keep_Control
  set Addrs_left   to "0101010101"
end vector

vector AddressL_1001001001
  initialize       to Keep_Control
  set Addrs_left   to "1001001001"
end vector

vector AddressL_0100100100
  initialize       to Keep_Control
  set Addrs_left   to "0100100100"
end vector

vector AddressL_0011001100
  initialize       to Keep_Control
  set Addrs_left   to "1010101010"
end vector

vector AddressL_0100010001
  initialize       to Keep_Control
  set Addrs_left   to "1010101010"
end vector

vector AddressL_1100110011
  initialize       to Keep_Control
  set Addrs_left   to "1100110011"
end vector

vector AddressL_1100111001
  initialize       to Keep_Control
  set Addrs_left   to "1100111001"
end vector

vector AddressL_1000010000
  initialize       to Keep_Control
  set Addrs_left   to "1000010000"
end vector

vector AddressL_1111111111
  initialize       to Keep_Control
  set Addrs_left   to "1111111111"
end vector

vector AddressL_1111111110
  initialize       to Keep_Control
  set Addrs_left   to "1111111110"
end vector

vector AddressL_1111101010
  initialize       to Keep_Control
  set Addrs_left   to "1111101010"
end vector

vector AddressR_1010101010
  initialize       to Keep_Control
  set Addrs_right  to "1010101010"
end vector

vector AddressR_0101010101
  initialize       to Keep_Control
  set Addrs_right  to "0101010101"
end vector

vector AddressR_1001001001
  initialize       to Keep_Control
  set Addrs_right  to "1001001001"
end vector

vector AddressR_0100100100
  initialize       to Keep_Control
  set Addrs_right  to "0100100100"
end vector

vector AddressR_0011001100
  initialize       to Keep_Control
  set Addrs_right  to "1010101010"
end vector

vector AddressR_0100010001
  initialize       to Keep_Control
  set Addrs_right  to "1010101010"
end vector

vector AddressR_1100110011
  initialize       to Keep_Control
  set Addrs_right  to "1100110011"
end vector

vector AddressR_1100111001
  initialize       to Keep_Control
  set Addrs_right  to "1100111001"
end vector

vector AddressR_0111101111
  initialize       to Keep_Control
  set Addrs_right  to "0111101111"
end vector

vector AddressR_1111111111
  initialize       to Keep_Control
  set Addrs_right  to "1111111111"
end vector

vector AddressR_1111111110
  initialize       to Keep_Control
  set Addrs_right  to "1111111110"
end vector

vector AddressR_0101011111
  initialize       to Keep_Control
  set Addrs_right  to "0101011111"
end vector


!+++++++++++++++ Data Vectors +++++++++++++++++!

vector DataL_2492W
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "2492"
end vector

vector DataL_4924W
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "4924"
end vector

vector DataL_aaaaW
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "aaaa"
end vector

vector DataL_5555W
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "5555"
end vector

vector DataL_1111W
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "1111"
end vector

vector DataL_ccccW
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "cccc"
end vector

vector DataL_3333W
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "3333"
end vector

vector DataL_0000W
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "0000"
end vector

vector DataL_2222W
  initialize       to Keep_Control
  drive Data_left
  set Data_left    to "2222"
end vector

vector DataL_0000R
  initialize       to Keep_Control
  receive Data_left
  set Data_left    to "0000"
end vector

vector DataL_2492R
  initialize       to Keep_Control
  receive Data_left
  set Data_left    to "2492"
end vector

vector DataL_4924R
  initialize       to Keep_Control
  receive Data_left
  set Data_left    to "4924"
end vector

vector DataL_aaaaR
  initialize       to Keep_Control
  receive Data_left
  set Data_left    to "aaaa"
end vector

vector DataL_5555R
  initialize       to Keep_Control
  receive Data_left
  set Data_left    to "5555"
end vector

vector DataL_1111R
  initialize       to Keep_Control
  receive Data_left
  set Data_left    to "1111"
end vector

vector DataL_ccccR
  initialize       to Keep_Control
  receive Data_left
  set Data_left    to "cccc"
end vector

vector DataL_xx55R
  initialize       to Keep_Control
  receive Data_left
  set Data_left    to "xx55"
end vector

vector DataR_55W
  initialize       to Keep_Control
  drive Data_right
  set Data_right   to "55"
end vector

vector DataR_ccW
  initialize       to Keep_Control
  drive Data_right
  set Data_right   to "cc"
end vector

vector DataR_11W
  initialize       to Keep_Control
  drive Data_right
  set Data_right   to "11"
end vector

vector DataR_aaW
  initialize       to Keep_Control
  drive Data_right
  set Data_right   to "aa"
end vector

vector DataR_49W
  initialize       to Keep_Control
  drive Data_right
  set Data_right   to "49"
end vector

vector DataR_24W
  initialize       to Keep_Control
  drive Data_right
  set Data_right   to "24"
end vector

vector DataR_24R
  initialize       to Keep_Control
  receive Data_right
  set Data_right   to "24"
end vector

vector DataR_49R
  initialize       to Keep_Control
  receive Data_right
  set Data_right   to "49"
end vector

vector DataR_aaR
  initialize       to Keep_Control
  receive Data_right
  set Data_right   to "aa"
end vector

vector DataR_55R
  initialize       to Keep_Control
  receive Data_right
  set Data_right   to "55"
end vector

vector DataR_11R
  initialize       to Keep_Control
  receive Data_right
  set Data_right   to "11"
end vector

vector DataR_ccR
  initialize       to Keep_Control
  receive Data_right
  set Data_right   to "cc"
end vector

vector DataR_92R
  initialize       to Keep_Control
  receive Data_right
  set Data_right   to "92"
end vector

vector DataR_33R
  initialize       to Keep_Control
  receive Data_right
  set Data_right   to "33"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector DataL_D0_0W
  initialize       to Keep_Control
  drive Data_left_D0
  set Data_left_D0    to "0"
end vector

vector DataL_D0_1W
  initialize       to Keep_Control
  drive Data_left_D0
  set Data_left_D0    to "1"
end vector

vector DataL_D0_0R
  initialize       to Keep_Control
  receive Data_left_D0
  set Data_left_D0    to "0"
end vector

vector DataL_D0_1R
  initialize       to Keep_Control
  receive Data_left_D0
  set Data_left_D0    to "1"
end vector

vector DataL_D1_0W
  initialize       to Keep_Control
  drive Data_left_D1
  set Data_left_D1    to "0"
end vector

vector DataL_D1_1W
  initialize       to Keep_Control
  drive Data_left_D1
  set Data_left_D1    to "1"
end vector

vector DataL_D1_0R
  initialize       to Keep_Control
  receive Data_left_D1
  set Data_left_D1    to "0"
end vector

vector DataL_D1_1R
  initialize       to Keep_Control
  receive Data_left_D1
  set Data_left_D1    to "1"
end vector

vector DataL_D2_0W
  initialize       to Keep_Control
  drive Data_left_D2
  set Data_left_D2    to "0"
end vector

vector DataL_D2_1W
  initialize       to Keep_Control
  drive Data_left_D2
  set Data_left_D2    to "1"
end vector

vector DataL_D2_0R
  initialize       to Keep_Control
  receive Data_left_D2
  set Data_left_D2    to "0"
end vector

vector DataL_D2_1R
  initialize       to Keep_Control
  receive Data_left_D2
  set Data_left_D2    to "1"
end vector

vector DataL_D3_0W
  initialize       to Keep_Control
  drive Data_left_D3
  set Data_left_D3    to "0"
end vector

vector DataL_D3_1W
  initialize       to Keep_Control
  drive Data_left_D3
  set Data_left_D3    to "1"
end vector

vector DataL_D3_0R
  initialize       to Keep_Control
  receive Data_left_D3
  set Data_left_D3    to "0"
end vector

vector DataL_D3_1R
  initialize       to Keep_Control
  receive Data_left_D3
  set Data_left_D3    to "1"
end vector

vector DataL_D4_0W
  initialize       to Keep_Control
  drive Data_left_D4
  set Data_left_D4    to "0"
end vector

vector DataL_D4_1W
  initialize       to Keep_Control
  drive Data_left_D4
  set Data_left_D4    to "1"
end vector

vector DataL_D4_0R
  initialize       to Keep_Control
  receive Data_left_D4
  set Data_left_D4    to "0"
end vector

vector DataL_D4_1R
  initialize       to Keep_Control
  receive Data_left_D4
  set Data_left_D4    to "1"
end vector

vector DataL_D5_0W
  initialize       to Keep_Control
  drive Data_left_D5
  set Data_left_D5    to "0"
end vector

vector DataL_D5_1W
  initialize       to Keep_Control
  drive Data_left_D5
  set Data_left_D5    to "1"
end vector

vector DataL_D5_0R
  initialize       to Keep_Control
  receive Data_left_D5
  set Data_left_D5    to "0"
end vector

vector DataL_D5_1R
  initialize       to Keep_Control
  receive Data_left_D5
  set Data_left_D5    to "1"
end vector

vector DataL_D6_0W
  initialize       to Keep_Control
  drive Data_left_D6
  set Data_left_D6    to "0"
end vector

vector DataL_D6_1W
  initialize       to Keep_Control
  drive Data_left_D6
  set Data_left_D6    to "1"
end vector

vector DataL_D6_0R
  initialize       to Keep_Control
  receive Data_left_D6
  set Data_left_D6    to "0"
end vector

vector DataL_D6_1R
  initialize       to Keep_Control
  receive Data_left_D6
  set Data_left_D6    to "1"
end vector

vector DataL_D7_0W
  initialize       to Keep_Control
  drive Data_left_D7
  set Data_left_D7    to "0"
end vector

vector DataL_D7_1W
  initialize       to Keep_Control
  drive Data_left_D7
  set Data_left_D7    to "1"
end vector

vector DataL_D7_0R
  initialize       to Keep_Control
  receive Data_left_D7
  set Data_left_D7    to "0"
end vector

vector DataL_D7_1R
  initialize       to Keep_Control
  receive Data_left_D7
  set Data_left_D7    to "1"
end vector

vector DataL_D8_0W
  initialize       to Keep_Control
  drive Data_left_D8
  set Data_left_D8    to "0"
end vector

vector DataL_D8_1W
  initialize       to Keep_Control
  drive Data_left_D8
  set Data_left_D8    to "1"
end vector

vector DataL_D8_0R
  initialize       to Keep_Control
  receive Data_left_D8
  set Data_left_D8    to "0"
end vector

vector DataL_D8_1R
  initialize       to Keep_Control
  receive Data_left_D8
  set Data_left_D8    to "1"
end vector

vector DataL_D9_0W
  initialize       to Keep_Control
  drive Data_left_D9
  set Data_left_D9    to "0"
end vector

vector DataL_D9_1W
  initialize       to Keep_Control
  drive Data_left_D9
  set Data_left_D9    to "1"
end vector

vector DataL_D9_0R
  initialize       to Keep_Control
  receive Data_left_D9
  set Data_left_D9    to "0"
end vector

vector DataL_D9_1R
  initialize       to Keep_Control
  receive Data_left_D9
  set Data_left_D9    to "1"
end vector

vector DataL_D10_0W
  initialize       to Keep_Control
  drive Data_left_D10
  set Data_left_D10    to "0"
end vector

vector DataL_D10_1W
  initialize       to Keep_Control
  drive Data_left_D10
  set Data_left_D10    to "1"
end vector

vector DataL_D10_0R
  initialize       to Keep_Control
  receive Data_left_D10
  set Data_left_D10    to "0"
end vector

vector DataL_D10_1R
  initialize       to Keep_Control
  receive Data_left_D10
  set Data_left_D10    to "1"
end vector

vector DataL_D11_0W
  initialize       to Keep_Control
  drive Data_left_D11
  set Data_left_D11    to "0"
end vector

vector DataL_D11_1W
  initialize       to Keep_Control
  drive Data_left_D11
  set Data_left_D11    to "1"
end vector

vector DataL_D11_0R
  initialize       to Keep_Control
  receive Data_left_D11
  set Data_left_D11    to "0"
end vector

vector DataL_D11_1R
  initialize       to Keep_Control
  receive Data_left_D11
  set Data_left_D11    to "1"
end vector

vector DataL_D12_0W
  initialize       to Keep_Control
  drive Data_left_D12
  set Data_left_D12    to "0"
end vector

vector DataL_D12_1W
  initialize       to Keep_Control
  drive Data_left_D12
  set Data_left_D12    to "1"
end vector

vector DataL_D12_0R
  initialize       to Keep_Control
  receive Data_left_D12
  set Data_left_D12    to "0"
end vector

vector DataL_D12_1R
  initialize       to Keep_Control
  receive Data_left_D12
  set Data_left_D12    to "1"
end vector

vector DataL_D13_0W
  initialize       to Keep_Control
  drive Data_left_D13
  set Data_left_D13    to "0"
end vector

vector DataL_D13_1W
  initialize       to Keep_Control
  drive Data_left_D13
  set Data_left_D13    to "1"
end vector

vector DataL_D13_0R
  initialize       to Keep_Control
  receive Data_left_D13
  set Data_left_D13    to "0"
end vector

vector DataL_D13_1R
  initialize       to Keep_Control
  receive Data_left_D13
  set Data_left_D13    to "1"
end vector

vector DataL_D14_0W
  initialize       to Keep_Control
  drive Data_left_D14
  set Data_left_D14    to "0"
end vector

vector DataL_D14_1W
  initialize       to Keep_Control
  drive Data_left_D14
  set Data_left_D14    to "1"
end vector

vector DataL_D14_0R
  initialize       to Keep_Control
  receive Data_left_D14
  set Data_left_D14    to "0"
end vector

vector DataL_D14_1R
  initialize       to Keep_Control
  receive Data_left_D14
  set Data_left_D14    to "1"
end vector

vector DataL_D15_0W
  initialize       to Keep_Control
  drive Data_left_D15
  set Data_left_D15    to "0"
end vector

vector DataL_D15_1W
  initialize       to Keep_Control
  drive Data_left_D15
  set Data_left_D15    to "1"
end vector

vector DataL_D15_0R
  initialize       to Keep_Control
  receive Data_left_D15
  set Data_left_D15    to "0"
end vector

vector DataL_D15_1R
  initialize       to Keep_Control
  receive Data_left_D15
  set Data_left_D15    to "1"
end vector

vector DataR_D0_0W
  initialize       to Keep_Control
  drive Data_right_D0
  set Data_right_D0   to "0"
end vector

vector DataR_D0_1W
  initialize       to Keep_Control
  drive Data_right_D0
  set Data_right_D0   to "1"
end vector

vector DataR_D0_0R
  initialize       to Keep_Control
  receive Data_right_D0
  set Data_right_D0   to "0"
end vector

vector DataR_D0_1R
  initialize       to Keep_Control
  receive Data_right_D0
  set Data_right_D0   to "1"
end vector

vector DataR_D1_0W
  initialize       to Keep_Control
  drive Data_right_D1
  set Data_right_D1   to "0"
end vector

vector DataR_D1_1W
  initialize       to Keep_Control
  drive Data_right_D1
  set Data_right_D1   to "1"
end vector

vector DataR_D1_0R
  initialize       to Keep_Control
  receive Data_right_D1
  set Data_right_D1   to "0"
end vector

vector DataR_D1_1R
  initialize       to Keep_Control
  receive Data_right_D1
  set Data_right_D1   to "1"
end vector

vector DataR_D2_0W
  initialize       to Keep_Control
  drive Data_right_D2
  set Data_right_D2   to "0"
end vector

vector DataR_D2_1W
  initialize       to Keep_Control
  drive Data_right_D2
  set Data_right_D2   to "1"
end vector

vector DataR_D2_0R
  initialize       to Keep_Control
  receive Data_right_D2
  set Data_right_D2   to "0"
end vector

vector DataR_D2_1R
  initialize       to Keep_Control
  receive Data_right_D2
  set Data_right_D2   to "1"
end vector

vector DataR_D3_0W
  initialize       to Keep_Control
  drive Data_right_D3
  set Data_right_D3   to "0"
end vector

vector DataR_D3_1W
  initialize       to Keep_Control
  drive Data_right_D3
  set Data_right_D3   to "1"
end vector

vector DataR_D3_0R
  initialize       to Keep_Control
  receive Data_right_D3
  set Data_right_D3   to "0"
end vector

vector DataR_D3_1R
  initialize       to Keep_Control
  receive Data_right_D3
  set Data_right_D3   to "1"
end vector

vector DataR_D4_0W
  initialize       to Keep_Control
  drive Data_right_D4
  set Data_right_D4   to "0"
end vector

vector DataR_D4_1W
  initialize       to Keep_Control
  drive Data_right_D4
  set Data_right_D4   to "1"
end vector

vector DataR_D4_0R
  initialize       to Keep_Control
  receive Data_right_D4
  set Data_right_D4   to "0"
end vector

vector DataR_D4_1R
  initialize       to Keep_Control
  receive Data_right_D4
  set Data_right_D4   to "1"
end vector

vector DataR_D5_0W
  initialize       to Keep_Control
  drive Data_right_D5
  set Data_right_D5   to "0"
end vector

vector DataR_D5_1W
  initialize       to Keep_Control
  drive Data_right_D5
  set Data_right_D5   to "1"
end vector

vector DataR_D5_0R
  initialize       to Keep_Control
  receive Data_right_D5
  set Data_right_D5   to "0"
end vector

vector DataR_D5_1R
  initialize       to Keep_Control
  receive Data_right_D5
  set Data_right_D5   to "1"
end vector

vector DataR_D6_0W
  initialize       to Keep_Control
  drive Data_right_D6
  set Data_right_D6   to "0"
end vector

vector DataR_D6_1W
  initialize       to Keep_Control
  drive Data_right_D6
  set Data_right_D6   to "1"
end vector

vector DataR_D6_0R
  initialize       to Keep_Control
  receive Data_right_D6
  set Data_right_D6   to "0"
end vector

vector DataR_D6_1R
  initialize       to Keep_Control
  receive Data_right_D6
  set Data_right_D6   to "1"
end vector

vector DataR_D7_0W
  initialize       to Keep_Control
  drive Data_right_D7
  set Data_right_D7   to "0"
end vector

vector DataR_D7_1W
  initialize       to Keep_Control
  drive Data_right_D7
  set Data_right_D7   to "1"
end vector

vector DataR_D7_0R
  initialize       to Keep_Control
  receive Data_right_D7
  set Data_right_D7   to "0"
end vector

vector DataR_D7_1R
  initialize       to Keep_Control
  receive Data_right_D7
  set Data_right_D7   to "1"
end vector

!++++++++++++++++ Subroutines +++++++++++++++++!
!

!  Subroutine: Write_Left_Side
!  This write cycle writes data on the 16 lines of the left side port.
sub  Write_Left_Side(Address,Data)
   execute  Address
   execute  Left_chip_enable
   execute  Left_write_enable
   execute  Data
   execute  Write_cycle_end_left
end sub

!  Subroutine: Write_Right_Side_lower
!  This write cycle writes data on the 8 lines of the right side port. Also
!  the data is written to the lower byte of the word.
sub  Write_Right_Side_lower(Address,Data)
   execute  Select_lower_byte
   execute  Address
   execute  Right_chip_enable
   execute  Right_write_enable
   execute  Data
   execute  Write_cycle_end_right
end sub

!  Subroutine: Write_Right_Side_upper
!  This write cycle writes data on the 8 lines of the right side port. Also
!  the data is written to the upper byte of the word.
sub  Write_Right_Side_upper(Address,Data)
   execute  Select_upper_byte
   execute  Address
   execute  Right_chip_enable
   execute  Right_write_enable
   execute  Data
   execute  Write_cycle_end_right
end sub

!  Subroutine: Read_Left_2byte
!  This subroutine reads data on the 16 data lines of the left side port.
sub  Read_Left_2byte(Address,Data)
   execute Address
   execute Word_enable
   execute Left_chip_enable
   execute Left_output_enable
   execute Data
   execute Left_chip_disable
   execute Word_disable
   execute Left_output_disable
end sub

!  Subroutine: Read_right_upper
!  This subroutine reads the upper byte contained at the address called in.
sub  Read_right_upper(Address,Data)
   execute Select_upper_byte
   execute Right_chip_enable
   execute Address
   execute Right_output_enable
   execute Data
   execute Right_output_disable
   execute Right_chip_disable
end sub

!  Subroutine: Read_right_lower
!  This subroutine reads the lower byte contained at the address called in.
sub  Read_right_lower(Address,Data)
   execute Select_lower_byte
   execute Right_chip_enable
   execute Address
   execute Right_output_enable
   execute Data
   execute Right_output_disable
   execute Right_chip_disable
end sub

!  Subroutine: Read_Left_high_byte
!  This subroutine reads data on the upper 8 bits of the data bus. The lower 8
!  bits of the data bus are put into a high impedance state.
sub  Read_Left_high_byte(Address,Data)
   execute Address
   execute Byte_high_enable
   execute Left_chip_enable
   execute Left_output_enable
   execute Data
   execute Left_chip_disable
   execute Byte_high_disable
   execute Left_output_disable
end sub

!  Subroutine: Read_Left_low_byte
!  This subroutine reads data on the lower 8 bits of the data bus. The upper 8
!  bits of the data bus are put into a high impedance state.
sub  Read_Left_low_byte(Address,Data)
   execute Address
   execute Byte_low_enable
   execute Left_chip_enable
   execute Left_output_enable
   execute Data
   execute Left_chip_disable
   execute Byte_low_disable
   execute Left_output_disable
end sub

!*****************************************************************************!
!************************ Vector Execution Section****************************!
!*****************************************************************************!

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest Left D0 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D0_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D0_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D0_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D0_1R)

end unit

unit   "awaretest Left D1 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D1_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D1_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D1_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D1_1R)

end unit

unit   "awaretest Left D2 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D2_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D2_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D2_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D2_1R)

end unit

unit   "awaretest Left D3 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D3_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D3_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D3_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D3_1R)

end unit

unit   "awaretest Left D4 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D4_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D4_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D4_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D4_1R)

end unit

unit   "awaretest Left D5 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D5_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D5_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D5_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D5_1R)

end unit

unit   "awaretest Left D6 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D6_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D6_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D6_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D6_1R)

end unit

unit   "awaretest Left D7 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D7_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D7_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D7_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D7_1R)

end unit

unit   "awaretest Left D8 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D8_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D8_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D8_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D8_1R)

end unit

unit   "awaretest Left D9 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D9_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D9_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D9_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D9_1R)

end unit

unit   "awaretest Left D10 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D10_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D10_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D10_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D10_1R)

end unit

unit   "awaretest Left D11 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D11_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D11_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D11_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D11_1R)

end unit

unit   "awaretest Left D12 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D12_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D12_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D12_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D12_1R)

end unit

unit   "awaretest Left D13 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D13_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D13_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D13_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D13_1R)

end unit

unit   "awaretest Left D14 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D14_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D14_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D14_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D14_1R)

end unit

unit   "awaretest Left D15 Test"

  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_D15_0W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D15_0R)

  call Write_Left_Side(AddressL_1010101010,DataL_D15_1W)
  call Read_Left_2byte(AddressL_1010101010,DataL_D15_1R)

end unit

unit   "awaretest Right D0 Test"

  execute Initial_Inputs

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D0_0W)
  call Read_right_lower(AddressR_1010101010,DataR_D0_0R)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D0_1W)
  call Read_right_lower(AddressR_1010101010,DataR_D0_1R)

end unit

unit   "awaretest Right D1 Test"

  execute Initial_Inputs

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D1_0W)
  call Read_right_lower(AddressR_1010101010,DataR_D1_0R)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D1_1W)
  call Read_right_lower(AddressR_1010101010,DataR_D1_1R)

end unit

unit   "awaretest Right D2 Test"

  execute Initial_Inputs

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D2_0W)
  call Read_right_lower(AddressR_1010101010,DataR_D2_0R)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D2_1W)
  call Read_right_lower(AddressR_1010101010,DataR_D2_1R)

end unit

unit   "awaretest Right D3 Test"

  execute Initial_Inputs

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D3_0W)
  call Read_right_lower(AddressR_1010101010,DataR_D3_0R)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D3_1W)
  call Read_right_lower(AddressR_1010101010,DataR_D3_1R)

end unit

unit   "awaretest Right D4 Test"

  execute Initial_Inputs

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D4_0W)
  call Read_right_lower(AddressR_1010101010,DataR_D4_0R)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D4_1W)
  call Read_right_lower(AddressR_1010101010,DataR_D4_1R)

end unit

unit   "awaretest Right D5 Test"

  execute Initial_Inputs

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D5_0W)
  call Read_right_lower(AddressR_1010101010,DataR_D5_0R)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D5_1W)
  call Read_right_lower(AddressR_1010101010,DataR_D5_1R)

end unit

unit   "awaretest Right D6 Test"

  execute Initial_Inputs

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D6_0W)
  call Read_right_lower(AddressR_1010101010,DataR_D6_0R)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D6_1W)
  call Read_right_lower(AddressR_1010101010,DataR_D6_1R)

end unit

unit   "awaretest Right D7 Test"

  execute Initial_Inputs

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D7_0W)
  call Read_right_lower(AddressR_1010101010,DataR_D7_0R)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_D7_1W)
  call Read_right_lower(AddressR_1010101010,DataR_D7_1R)

end unit

unit "Test Bus and control pins"
!
! This unit tests the address bus, data bus, and bus control pins.            !
!
  execute Initial_Inputs
  call Write_Left_Side(AddressL_1010101010,DataL_2492W)
  call Write_Left_Side(AddressL_0101010101,DataL_4924W)
  call Write_Left_Side(AddressL_1001001001,DataL_aaaaW)
  call Write_Left_Side(AddressL_0100100100,DataL_5555W)
  call Write_Left_Side(AddressL_0011001100,DataL_1111W)
  call Write_Left_Side(AddressL_0100010001,DataL_ccccW)

  call Read_Left_2byte(AddressL_1010101010,DataL_2492R)
  call Read_Left_2byte(AddressL_0101010101,DataL_4924R)
  call Read_Left_2byte(AddressL_1001001001,DataL_aaaaR)
  call Read_Left_2byte(AddressL_0100100100,DataL_5555R)
  call Read_Left_2byte(AddressL_0011001100,DataL_1111R)
  call Read_Left_2byte(AddressL_0100010001,DataL_ccccR)

  call Write_Right_Side_lower(AddressR_1010101010,DataR_ccW)
  call Write_Right_Side_lower(AddressR_0101010101,DataR_11W)
  call Write_Right_Side_lower(AddressR_1001001001,DataR_55W)
  call Write_Right_Side_lower(AddressR_0100100100,DataR_aaW)
  call Write_Right_Side_lower(AddressR_0011001100,DataR_49W)
  call Write_Right_Side_upper(AddressR_0011001100,DataR_55W)
  call Write_Right_Side_lower(AddressR_0100010001,DataR_24W)

  call Read_right_lower(AddressR_1010101010,DataR_ccR)
  call Read_right_lower(AddressR_0101010101,DataR_11R)
  call Read_right_lower(AddressR_1001001001,DataR_55R)
  call Read_right_lower(AddressR_0100100100,DataR_aaR)
  call Read_right_upper(AddressR_0011001100,DataR_55R)
  call Read_right_lower(AddressR_0011001100,DataR_49R)
  call Read_right_lower(AddressR_0100010001,DataR_24R)
end unit


unit "Test Busy lines"
  execute Initial_Inputs

  execute BusyR_false
  execute AddressL_1100110011
  execute AddressR_1100110011
  execute BusyR_true
  execute AddressL_1000010000
  execute BusyR_false

  execute BusyL_false
  execute AddressR_1100111001
  execute AddressL_1100111001
  execute BusyL_true
  execute AddressR_0111101111
  execute BusyL_false
end unit


unit "Test INTX lines"
  execute Initial_Inputs

  execute AddressL_1111111111
  execute Left_chip_enable
  execute INTR_false
  execute Left_write_enable
  execute INTR_true
  execute DataL_3333W
  execute Write_cycle_end_left

  execute Select_lower_byte
  execute Right_chip_enable
  execute AddressR_1111111111
  execute Right_output_enable
  execute INTR_false
  execute DataR_33R
  execute Right_output_disable
  execute Right_chip_disable


  execute AddressR_1111111110
  execute Right_chip_enable
  execute INTL_false
  execute Right_write_enable
  execute INTL_true
  execute DataR_55W
  execute Write_cycle_end_right

  execute AddressL_1111111110
  execute Word_enable
  execute Left_chip_enable
  execute Left_output_enable
  execute INTL_false
  execute DataL_xx55R
  execute Left_chip_disable
  execute Word_disable
  execute Left_output_disable
end unit

unit "Test chip enables"
  execute Initial_Inputs

!!sub  Write_Left_Side(AddressL_1111101010,DataL_2492W)
   execute  AddressL_1111101010
   execute  Left_chip_enable
   execute  Left_write_enable
   execute  DataL_2492W
   execute  Write_cycle_end_left
!!end sub
!!sub  Read_Left_2byte(AddressL_1111101010,DataL_2492R)
   execute AddressL_1111101010
   execute Word_enable
   execute Left_chip_enable
   execute Left_output_enable
   execute DataL_2492R
   execute Left_chip_disable
   execute Word_disable
   execute Left_output_disable
!!end sub
!!sub  Write_Left_Side_disabled(AddressL_1111101010,DataL_2222W)
   execute  AddressL_1111101010
   execute  Left_chip_disable       !Disable writing to the left side of the
   execute  Left_write_enable       !chip.
   execute  DataL_2222W
   execute  Write_cycle_end_left
!!end sub
!!sub  Read_Left_2byte(AddressL_1111101010,DataL_2492R)
   execute AddressL_1111101010
   execute Word_enable
   execute Left_chip_enable
   execute Left_output_enable
   execute DataL_2492R              !Data should not have changed.
   execute Left_chip_disable
   execute Word_disable
   execute Left_output_disable
!!end sub
!!sub  Write_Right_Side_lower(AddressR_0101011111,DataR_aaW)
   execute  Select_lower_byte
   execute  AddressR_0101011111
   execute  Right_chip_enable
   execute  Right_write_enable
   execute  DataR_aaW
   execute  Write_cycle_end_right
!!end sub
!!sub  Read_right_lower(AddressR_0101011111,DataR_aaR)
   execute Select_lower_byte
   execute Right_chip_enable
   execute AddressR_0101011111
   execute Right_output_enable
   execute DataR_aaR
   execute Right_output_disable
   execute Right_chip_disable
!!end sub
!!sub  Write_Right_Side_lower_disabled(AddressR_0101011111,DataR_55W)
   execute  Right_chip_disable       !Disable writing to the right side of the
   execute  Select_lower_byte        !chip.
   execute  AddressR_0101011111
   execute  Right_chip_enable
   execute  Right_write_enable
   execute  DataR_aaW
   execute  Write_cycle_end_right
!!end sub
!!sub  Read_right_lower(AddressR_0101011111,DataR_aaR)
   execute Select_lower_byte
   execute Right_chip_enable
   execute AddressR_0101011111
   execute Right_output_enable
   execute DataR_aaR                 !The last write was done with the chip
   execute Right_output_disable      !disabled, therefore the data should
   execute Right_chip_disable        !still be aa.
!!end sub
end unit

unit disable test
!
!This disable unit tests the disabling ability of the byte high and low
!enable pins (BHE and BLE).
!
  execute Initial_Inputs

  call Write_Left_Side(AddressL_1010101010,DataL_0000W)
  call Read_Left_high_byte(AddressL_1010101010,DataL_0000R)
  call Write_Left_Side(AddressL_1010101010,DataL_1111W)
  call Read_Left_high_byte(AddressL_1010101010,DataL_1111R)

  call Write_Left_Side(AddressL_1010101010,DataL_0000W)
  call Read_Left_low_byte(AddressL_1010101010,DataL_0000R)
  call Write_Left_Side(AddressL_1010101010,DataL_1111W)
  call Read_Left_low_byte(AddressL_1010101010,DataL_1111R)
end unit
