!!!!    6    0    1  986844383  V1dd4                                         

! Device           : 8168
! Function         : Static RAM 3-state 4k x 4
! revision         : B.01.00
! safeguard        : high_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

!warning "Pull-ups are required to test high-impedance outputs."
!warning "Pins 12, 13, 14, 15 require pull ups."

vector cycle 1000n
receive delay 900n

assign    VCC            to pins   20
assign    GND            to pins   10

assign    Address        to pins   16,17,18,19,1,2,3,4,8,7
assign    Address        to pins 6,5

assign    Data           to pins   12,13,14,15
assign    Data_D0        to pins   15   !AT Added for minimum pin test.
assign    Data_D1        to pins   14   !AT Added for minimum pin test.
assign    Data_D2        to pins   13   !AT Added for minimum pin test.
assign    Data_D3        to pins   12   !AT Added for minimum pin test.

assign    Chip_select_bar     to pins   9
assign    Write_enable_bar    to pins   11


family    TTL


power          VCC, GND

inputs         Address, Chip_select_bar, Write_enable_bar

bidirectional  Data
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.

disable   Data      with Chip_select_bar     to   "1"
disable   Data      with Write_enable_bar    to   "0"

when Chip_select_bar is "1" inactive Data
when Write_enable_bar is "0" inputs Data
when Write_enable_bar is "1" outputs Data

trace Data to Address, Chip_select_bar, Write_enable_bar

set load on groups  Data  to pull up

!***************************************************************
!***************************************************************

vector    Read_enable
   set  Address             to   "kkkkkkkkkkkk"
   set  Write_enable_bar    to   "1"
   set  Chip_select_bar     to   "0"
end vector

vector    Write_enable
   set  Address             to   "kkkkkkkkkkkk"
   set  Chip_select_bar     to   "0"
   set  Write_enable_bar    to   "0"
end vector

vector    Write_enable_CS_false
   set  Address             to   "kkkkkkkkkkkk"
   set  Chip_select_bar     to   "1"
   set  Write_enable_bar    to   "0"
end vector

vector   Read_enable_CS_false
   set   Address           to    "kkkkkkkkkkkk"
   set   Chip_select_bar   to    "1"
   set   Write_enable_bar  to    "1"
end   vector


vector    Disable
   set  Chip_select_bar     to   "1"
   set  Write_enable_bar    to   "1"
end vector

vector    Address_000000000000
   initialize to  Disable
   set  Address   to   "000000000000"
end vector

vector    Address_000000000001
   initialize to  Disable
   set  Address   to   "000000000001"
end vector

vector    Address_000000000011
   initialize to  Disable
   set  Address   to   "000000000011"
end vector

vector    Address_000000000111
   initialize to  Disable
   set  Address   to   "000000000111"
end vector

vector    Address_000000001111
   initialize to  Disable
   set  Address   to   "000000001111"
end vector

vector    Address_000000011111
   initialize to  Disable
   set  Address   to   "000000011111"
end vector

vector    Address_000000111111
   initialize to  Disable
   set  Address   to   "000000111111"
end vector

vector    Address_000001111111
   initialize to  Disable
   set  Address   to   "000001111111"
end vector

vector    Address_000011111111
   initialize to  Disable
   set  Address   to   "000011111111"
end vector

vector    Address_000111111111
   initialize to  Disable
   set  Address   to   "000111111111"
end vector

vector    Address_001111111111
   initialize to  Disable
   set  Address   to   "001111111111"
end vector

vector    Address_011111111111
   initialize to  Disable
   set  Address   to   "011111111111"
end vector

vector    Address_111111111111
   initialize to  Disable
   set  Address   to   "111111111111"
end vector

vector    Data_write_0000
   initialize to  Write_enable
   drive     Data
   set  Data       to   "0000"
end vector

vector    Data_write_0001
   initialize to  Write_enable
   drive     Data
   set  Data       to   "0001"
end vector

vector    Data_write_0011
   initialize to  Write_enable
   drive     Data
   set  Data       to   "0011"
end vector

vector    Data_write_0111
   initialize to  Write_enable
   drive     Data
   set  Data       to   "0111"
end vector

vector    Data_write_1111
   initialize to  Write_enable
   drive     Data
   set  Data       to   "1111"
end vector

vector    Data_write_1110
   initialize to  Write_enable
   drive     Data
   set  Data       to   "1110"
end vector

vector    Data_write_1100
   initialize to  Write_enable
   drive     Data
   set  Data       to   "1100"
end vector

vector    Data_write_1000
   initialize to  Write_enable
   drive     Data
   set  Data       to   "1000"
end vector

vector    Data_write_1010
   initialize to  Write_enable
   drive     Data
   set  Data       to   "1010"
end vector

vector    Data_write_0010
   initialize to  Write_enable
   drive     Data
   set  Data       to   "0010"
end vector

vector    Data_write_0110
   initialize to  Write_enable
   drive     Data
   set  Data       to   "0110"
end vector

vector    Data_write_0101
   initialize to  Write_enable
   drive     Data
   set  Data       to   "0101"
end vector

vector    Data_write_1101
   initialize to  Write_enable
   drive     Data
   set  Data       to   "1101"
end vector

vector    Data_write_1001
   initialize to  Write_enable
   drive     Data
   set  Data       to   "1001"
end vector

vector    Data_read_0000
   initialize to  Read_enable
   receive   Data
   set  Data       to   "0000"
end vector

vector    Data_read_0001
   initialize to  Read_enable
   receive   Data
   set  Data       to   "0001"
end vector

vector    Data_read_0011
   initialize to  Read_enable
   receive   Data
   set  Data       to   "0011"
end vector

vector    Data_read_0111
   initialize to  Read_enable
   receive   Data
   set  Data       to   "0111"
end vector

vector    Data_read_1111
   initialize to  Read_enable
   receive   Data
   set  Data       to   "1111"
end vector

vector    Data_read_1110
   initialize to  Read_enable
   receive   Data
   set  Data       to   "1110"
end vector

vector    Data_read_1100
   initialize to  Read_enable
   receive   Data
   set  Data       to   "1100"
end vector

vector    Data_read_1000
   initialize to  Read_enable
   receive   Data
   set  Data       to   "1000"
end vector

vector    Data_read_1010
   initialize to  Read_enable
   receive   Data
   set  Data       to   "1010"
end vector

vector    Data_read_0010
   initialize to  Read_enable
   receive   Data
   set  Data       to   "0010"
end vector

vector    Data_read_0110
   initialize to  Read_enable
   receive   Data
   set  Data       to   "0110"
end vector

vector    Data_read_0101
   initialize to  Read_enable
   receive   Data
   set  Data       to   "0101"
end vector

vector    Data_read_1101
   initialize to  Read_enable
   receive   Data
   set  Data       to   "1101"
end vector

vector    Data_read_1001
   initialize to  Read_enable
   receive   Data
   set  Data       to   "1001"
end vector

vector   Data_read_0000_CS_false
   receive Data
   set  Address          to "kkkkkkkkkkkk"
   set  Chip_select_bar  to "k"
   set  Write_enable_bar to "1"
   set  Data             to "0000"
end vector

vector   Data_read_1111_CS_false
   receive Data
   set  Address          to "kkkkkkkkkkkk"
   set  Chip_select_bar  to "1"
   set  Write_enable_bar to "1"
   set  Data             to "1111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Data_write_D0_0
   initialize to  Write_enable
   drive     Data_D0
   set  Data_D0    to   "0"
end vector

vector    Data_write_D0_1
   initialize to  Write_enable
   drive     Data_D0
   set  Data_D0    to   "1"
end vector

vector    Data_write_D1_0
   initialize to  Write_enable
   drive     Data_D1
   set  Data_D1    to   "0"
end vector

vector    Data_write_D1_1
   initialize to  Write_enable
   drive     Data_D1
   set  Data_D1    to   "1"
end vector

vector    Data_write_D2_0
   initialize to  Write_enable
   drive     Data_D2
   set  Data_D2    to   "0"
end vector

vector    Data_write_D2_1
   initialize to  Write_enable
   drive     Data_D2
   set  Data_D2    to   "1"
end vector

vector    Data_write_D3_0
   initialize to  Write_enable
   drive     Data_D3
   set  Data_D3    to   "0"
end vector

vector    Data_write_D3_1
   initialize to  Write_enable
   drive     Data_D3
   set  Data_D3    to   "1"
end vector

vector    Data_read_D0_0
   initialize to  Read_enable
   receive   Data_D0
   set  Data_D0    to   "0"
end vector

vector    Data_read_D0_1
   initialize to  Read_enable
   receive   Data_D0
   set  Data_D0    to   "1"
end vector

vector    Data_read_D1_0
   initialize to  Read_enable
   receive   Data_D1
   set  Data_D1    to   "0"
end vector

vector    Data_read_D1_1
   initialize to  Read_enable
   receive   Data_D1
   set  Data_D1    to   "1"
end vector

vector    Data_read_D2_0
   initialize to  Read_enable
   receive   Data_D2
   set  Data_D2    to   "0"
end vector

vector    Data_read_D2_1
   initialize to  Read_enable
   receive   Data_D2
   set  Data_D2    to   "1"
end vector

vector    Data_read_D3_0
   initialize to  Read_enable
   receive   Data_D3
   set  Data_D3    to   "0"
end vector

vector    Data_read_D3_1
   initialize to  Read_enable
   receive   Data_D3
   set  Data_D3    to   "1"
end vector

!***************************************************************
!***************************************************************

sub  Write_data (Address, Data)
   execute   Address
   execute   Data
   execute   Disable
end sub

sub  Read_data (Address, Data)
   execute   Address
   execute   Data
   execute   Disable
end sub


!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

   call Write_data (Address_000000000000, Data_write_D0_0)
   call Read_data (Address_000000000000, Data_read_D0_0)

   call Write_data (Address_000000000000, Data_write_D0_1)
   call Read_data (Address_000000000000, Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

   call Write_data (Address_000000000000, Data_write_D1_0)
   call Read_data (Address_000000000000, Data_read_D1_0)

   call Write_data (Address_000000000000, Data_write_D1_1)
   call Read_data (Address_000000000000, Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

   call Write_data (Address_000000000000, Data_write_D2_0)
   call Read_data (Address_000000000000, Data_read_D2_0)

   call Write_data (Address_000000000000, Data_write_D2_1)
   call Read_data (Address_000000000000, Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

   call Write_data (Address_000000000000, Data_write_D3_0)
   call Read_data (Address_000000000000, Data_read_D3_0)

   call Write_data (Address_000000000000, Data_write_D3_1)
   call Read_data (Address_000000000000, Data_read_D3_1)

end unit

unit "RAM test"
   call Write_data (Address_000000000000, Data_write_0000)
   call Write_data (Address_000000000001, Data_write_0001)
   call Write_data (Address_000000000011, Data_write_0011)
   call Write_data (Address_000000000111, Data_write_0111)
   call Write_data (Address_000000001111, Data_write_1111)
   call Write_data (Address_000000011111, Data_write_1110)
   call Write_data (Address_000000111111, Data_write_1100)
   call Write_data (Address_000001111111, Data_write_1000)
   call Write_data (Address_000011111111, Data_write_1010)
   call Write_data (Address_000111111111, Data_write_0010)
   call Write_data (Address_001111111111, Data_write_0110)
   call Write_data (Address_011111111111, Data_write_0010)
   call Write_data (Address_111111111111, Data_write_0110)


   call Read_data (Address_000000000000, Data_read_0000)
   call Read_data (Address_000000000001, Data_read_0001)
   call Read_data (Address_000000000011, Data_read_0011)
   call Read_data (Address_000000000111, Data_read_0111)
   call Read_data (Address_000000001111, Data_read_1111)
   call Read_data (Address_000000011111, Data_read_1110)
   call Read_data (Address_000000111111, Data_read_1100)
   call Read_data (Address_000001111111, Data_read_1000)
   call Read_data (Address_000011111111, Data_read_1010)
   call Read_data (Address_000111111111, Data_read_0010)
   call Read_data (Address_001111111111, Data_read_0110)
   call Read_data (Address_011111111111, Data_read_0010)
   call Read_data (Address_111111111111, Data_read_0110)


   call Write_data (Address_000000000000, Data_write_1111)
   call Write_data (Address_000000000001, Data_write_1110)
   call Write_data (Address_000000000011, Data_write_1100)
   call Write_data (Address_000000000111, Data_write_1000)
   call Write_data (Address_000000001111, Data_write_0000)
   call Write_data (Address_000000011111, Data_write_0001)
   call Write_data (Address_000000111111, Data_write_0011)
   call Write_data (Address_000001111111, Data_write_0111)
   call Write_data (Address_000011111111, Data_write_0101)
   call Write_data (Address_000111111111, Data_write_1101)
   call Write_data (Address_001111111111, Data_write_1001)
   call Write_data (Address_011111111111, Data_write_1101)
   call Write_data (Address_111111111111, Data_write_1001)


   call Read_data (Address_000000000000, Data_read_1111)
   call Read_data (Address_000000000001, Data_read_1110)
   call Read_data (Address_000000000011, Data_read_1100)
   call Read_data (Address_000000000111, Data_read_1000)
   call Read_data (Address_000000001111, Data_read_0000)
   call Read_data (Address_000000011111, Data_read_0001)
   call Read_data (Address_000000111111, Data_read_0011)
   call Read_data (Address_000001111111, Data_read_0111)
   call Read_data (Address_000011111111, Data_read_0101)
   call Read_data (Address_000111111111, Data_read_1101)
   call Read_data (Address_001111111111, Data_read_1001)
   call Read_data (Address_011111111111, Data_read_1101)
   call Read_data (Address_111111111111, Data_read_1001)
end unit



unit "Test_chip_select"

   execute   Address_000000000000
   execute   Data_write_0000

   execute  Data_read_1111_CS_false


end unit

!    End of test