!!!!    6    0    1  986224618  Vb24a                                         

! Device           : CY7C122
! Function         : Static RAM 256_by_4
! revision         : B.01.00
! safeguard        : high_out_hcmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

warning  " This device has outputs that can be set in the high   "
warning  "   impedance state.  In order to test OEbar (pin 18)   "
warning  "   pullups are needed on Data_Out (pins 16,14,12,10).  "


sequential

receive delay 400n
vector cycle  500n

assign   VDD         to pins  22
assign   VSS         to pins  8


assign   A7_A0       to pins  7,6,5,21,1,2,3,4
assign   Data_In     to pins  15,13,11,9
assign   DI_3        to pins  15
assign   DI_2        to pins  13
assign   DI_1        to pins  11
assign   DI_0        to pins  9

assign   CS2_CS1     to pins  17,19
assign   WEbar       to pins  20
assign   OEbar       to pins  18
assign   Data_Out    to pins  16,14,12,10
assign   DO_3        to pins  16
assign   DO_2        to pins  14
assign   DO_1        to pins  12
assign   DO_0        to pins  10


family   CMOS

power          VDD,VSS

inputs         A7_A0,Data_In,CS2_CS1,WEbar,OEbar
inputs         DI_3, DI_2, DI_1, DI_0

outputs        Data_Out
outputs        DO_3, DO_2, DO_1, DO_0

disable        Data_Out  with  CS2_CS1 to "0X"
disable        Data_Out  with  CS2_CS1 to "X1"
disable        Data_Out  with  WEbar   to "0"
disable        Data_Out  with  OEbar   to "1"

when CS2_CS1 is "0X" inactive Data_Out
when CS2_CS1 is "X1" inactive Data_Out
when WEbar   is "1"   outputs Data_Out
when OEbar   is "1"  inactive Data_Out

trace DO_3 to  A7_A0,CS2_CS1,WEbar,OEbar,DI_3
trace DO_2 to  A7_A0,CS2_CS1,WEbar,OEbar,DI_2
trace DO_1 to  A7_A0,CS2_CS1,WEbar,OEbar,DI_1
trace DO_0 to  A7_A0,CS2_CS1,WEbar,OEbar,DI_0
!***************************************************************
!***************************************************************

vector   Initialize
   set   A7_A0       to "00000000"
   set   CS2_CS1     to "10"
   set   WEbar       to "1"
   set   OEbar       to "0"
   set   Data_In     to "0000"
end vector

vector   Keep_inputs
   set   A7_A0       to "kkkkkkkk"
   set   Data_In     to "kkkk"
   set   CS2_CS1     to "kk"
   set   OEbar       to "k"
   set   WEbar       to "k"
end vector

vector End_cycle
   set A7_A0         to "kkkkkkkk"
   set Data_In       to "kkkk"
   set CS2_CS1       to "kk"
   set OEbar         to "k"
   set WEbar         to "1"
end vector

vector Add_00000000
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "00000000"
end vector

vector Add_00000001
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "00000001"
end vector

vector Add_00000010
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "00000010"
end vector

vector Add_00000100
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "00000100"
end vector

vector Add_00001000
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "00001000"
end vector

vector Add_00010000
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "00010000"
end vector

vector Add_00100000
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "00100000"
end vector

vector Add_01000000
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "01000000"
end vector

vector Add_10000000
  initialize to Keep_inputs
  set WEbar to "1"
  set A7_A0 to "10000000"
end vector

vector Data_0101
  initialize to Keep_inputs
  set WEbar to "0"
  set Data_In to "0101"
end vector

vector Data_1010
  initialize to Keep_inputs
  set WEbar to "0"
  set Data_In to "1010"
end vector

vector Data_1111_CS1bar_false
  initialize to Keep_inputs
  set CS2_CS1   to "11"
  set WEbar to "0"
  set Data_In to "0000"
end vector

vector Data_1111_CS2_false
  initialize to Keep_inputs
  set CS2_CS1   to "00"
  set WEbar to "0"
  set Data_In to "0000"
end vector

vector Data_0000
  initialize to Keep_inputs
  set WEbar to "0"
  set Data_In to "0000"
end vector


! output vectors


vector Output_0101
  initialize to Keep_inputs
  set Data_Out to "0101"
end vector

vector Output_1010
  initialize to Keep_inputs
  set Data_Out to "1010"
end vector

vector Output_0000
  initialize to Keep_inputs
  set Data_Out to "0000"
end vector

vector Output_ZZZZ
  initialize to Keep_inputs
  set Data_Out to "1111"
end vector

vector CS1bar_true
   initialize to Keep_inputs
   set CS2_CS1 to "10"
end vector

vector CS1bar_false
   initialize to Keep_inputs
   set CS2_CS1 to "11"
end vector

vector CS2_true
   initialize to Keep_inputs
   set CS2_CS1 to "10"
end vector

vector CS2_false
   initialize to Keep_inputs
   set CS2_CS1 to "00"
end vector

vector OEbar_false
  initialize to Keep_inputs
  set OEbar to "1"
end vector

vector WEbar_false
  initialize to Keep_inputs
  set WEbar to "1"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Initialize_DI_0
   set   A7_A0       to "00000000"
   set   CS2_CS1     to "10"
   set   WEbar       to "1"
   set   OEbar       to "0"
   set   DI_0        to "0"
end vector

vector   Initialize_DI_1
   set   A7_A0       to "00000000"
   set   CS2_CS1     to "10"
   set   WEbar       to "1"
   set   OEbar       to "0"
   set   DI_1        to "0"
end vector

vector   Initialize_DI_2
   set   A7_A0       to "00000000"
   set   CS2_CS1     to "10"
   set   WEbar       to "1"
   set   OEbar       to "0"
   set   DI_2        to "0"
end vector

vector   Initialize_DI_3
   set   A7_A0       to "00000000"
   set   CS2_CS1     to "10"
   set   WEbar       to "1"
   set   OEbar       to "0"
   set   DI_3        to "0"
end vector

vector   Keep_inputs_DI_0
   set   A7_A0       to "kkkkkkkk"
   set   DI_0        to "k"
   set   CS2_CS1     to "kk"
   set   OEbar       to "k"
   set   WEbar       to "k"
end vector

vector   Keep_inputs_DI_1
   set   A7_A0       to "kkkkkkkk"
   set   DI_1        to "k"
   set   CS2_CS1     to "kk"
   set   OEbar       to "k"
   set   WEbar       to "k"
end vector

vector   Keep_inputs_DI_2
   set   A7_A0       to "kkkkkkkk"
   set   DI_2        to "k"
   set   CS2_CS1     to "kk"
   set   OEbar       to "k"
   set   WEbar       to "k"
end vector

vector   Keep_inputs_DI_3
   set   A7_A0       to "kkkkkkkk"
   set   DI_3        to "k"
   set   CS2_CS1     to "kk"
   set   OEbar       to "k"
   set   WEbar       to "k"
end vector

vector End_cycle_DI_0
   set A7_A0         to "kkkkkkkk"
   set DI_0          to "k"
   set CS2_CS1       to "kk"
   set OEbar         to "k"
   set WEbar         to "1"
end vector

vector End_cycle_DI_1
   set A7_A0         to "kkkkkkkk"
   set DI_1          to "k"
   set CS2_CS1       to "kk"
   set OEbar         to "k"
   set WEbar         to "1"
end vector

vector End_cycle_DI_2
   set A7_A0         to "kkkkkkkk"
   set DI_2          to "k"
   set CS2_CS1       to "kk"
   set OEbar         to "k"
   set WEbar         to "1"
end vector

vector End_cycle_DI_3
   set A7_A0         to "kkkkkkkk"
   set DI_3          to "k"
   set CS2_CS1       to "kk"
   set OEbar         to "k"
   set WEbar         to "1"
end vector

vector Add_0_DI_0
  initialize to Keep_inputs_DI_0
  set WEbar          to "1"
  set A7_A0          to "00000000"
end vector

vector Add_0_DI_1
  initialize to Keep_inputs_DI_1
  set WEbar          to "1"
  set A7_A0          to "00000000"
end vector

vector Add_0_DI_2
  initialize to Keep_inputs_DI_2
  set WEbar          to "1"
  set A7_A0          to "00000000"
end vector

vector Add_0_DI_3
  initialize to Keep_inputs_DI_3
  set WEbar          to "1"
  set A7_A0          to "00000000"
end vector

vector Data_DI_0_0
  initialize to Keep_inputs_DI_0
  set WEbar          to "0"
  set DI_0           to "0"
end vector

vector Data_DI_0_1
  initialize to Keep_inputs_DI_0
  set WEbar          to "0"
  set DI_0           to "1"
end vector

vector Data_DI_1_0
  initialize to Keep_inputs_DI_1
  set WEbar          to "0"
  set DI_1           to "0"
end vector

vector Data_DI_1_1
  initialize to Keep_inputs_DI_1
  set WEbar          to "0"
  set DI_1           to "1"
end vector

vector Data_DI_2_0
  initialize to Keep_inputs_DI_2
  set WEbar          to "0"
  set DI_2           to "0"
end vector

vector Data_DI_2_1
  initialize to Keep_inputs_DI_2
  set WEbar          to "0"
  set DI_2           to "1"
end vector

vector Data_DI_3_0
  initialize to Keep_inputs_DI_3
  set WEbar          to "0"
  set DI_3           to "0"
end vector

vector Data_DI_3_1
  initialize to Keep_inputs_DI_3
  set WEbar          to "0"
  set DI_3           to "1"
end vector

vector Output_DO_0_0
  initialize to Keep_inputs_DI_0
  set DO_0           to "0"
end vector

vector Output_DO_0_1
  initialize to Keep_inputs_DI_0
  set DO_0           to "1"
end vector

vector Output_DO_1_0
  initialize to Keep_inputs_DI_1
  set DO_1           to "0"
end vector

vector Output_DO_1_1
  initialize to Keep_inputs_DI_1
  set DO_1           to "1"
end vector

vector Output_DO_2_0
  initialize to Keep_inputs_DI_2
  set DO_2           to "0"
end vector

vector Output_DO_2_1
  initialize to Keep_inputs_DI_2
  set DO_2           to "1"
end vector

vector Output_DO_3_0
  initialize to Keep_inputs_DI_3
  set DO_3           to "0"
end vector

vector Output_DO_3_1
  initialize to Keep_inputs_DI_3
  set DO_3           to "1"
end vector

!***************************************************************
!*******************  subroutine section  **********************

sub Write_cycle (Add,Data)
   execute Add
   execute Data
   execute End_cycle
end sub

sub Read_cycle  (Add,Out)
   execute Add
   execute Out
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_cycle" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_cycle" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Out). This reference can be modified in the
!AT call statement.

sub  Write_cycle_Dx (Add_Dx, Data_Dx, End_cycle_Dx)
   execute Add_Dx
   execute Data_Dx
   execute End_cycle_Dx
end sub

!****************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

   execute Initialize_DI_0
   call Write_cycle_Dx (Add_0_DI_0, Data_DI_0_0, End_cycle_DI_0)
   call Read_cycle   (Add_0_DI_0, Output_DO_0_0)

   call Write_cycle_Dx (Add_0_DI_0, Data_DI_0_1, End_cycle_DI_0)
   call Read_cycle   (Add_0_DI_0, Output_DO_0_1)

end unit

unit   "awaretest D1 Test"

   execute Initialize_DI_1
   call Write_cycle_Dx (Add_0_DI_1, Data_DI_1_0, End_cycle_DI_1)
   call Read_cycle   (Add_0_DI_1, Output_DO_1_0)

   call Write_cycle_Dx (Add_0_DI_1, Data_DI_1_1, End_cycle_DI_1)
   call Read_cycle   (Add_0_DI_1, Output_DO_1_1)

end unit

unit   "awaretest D2 Test"

   execute Initialize_DI_2
   call Write_cycle_Dx (Add_0_DI_2, Data_DI_2_0, End_cycle_DI_2)
   call Read_cycle   (Add_0_DI_2, Output_DO_2_0)

   call Write_cycle_Dx (Add_0_DI_2, Data_DI_2_1, End_cycle_DI_2)
   call Read_cycle   (Add_0_DI_2, Output_DO_2_1)

end unit

unit   "awaretest D3 Test"

   execute Initialize_DI_3
   call Write_cycle_Dx (Add_0_DI_3, Data_DI_3_0, End_cycle_DI_3)
   call Read_cycle   (Add_0_DI_3, Output_DO_3_0)

   call Write_cycle_Dx (Add_0_DI_3, Data_DI_3_1, End_cycle_DI_3)
   call Read_cycle   (Add_0_DI_3, Output_DO_3_1)

end unit

unit  "unit1, Test Address and Data lines"
   execute Initialize
   call Write_cycle  (Add_00000000,Data_0101)
   call Write_cycle  (Add_00000001,Data_0101)
   call Write_cycle  (Add_00000010,Data_0101)
   call Write_cycle  (Add_00000100,Data_0101)
   call Write_cycle  (Add_00001000,Data_0101)
   call Write_cycle  (Add_00010000,Data_0101)
   call Write_cycle  (Add_00100000,Data_0101)
   call Write_cycle  (Add_01000000,Data_0101)
   call Write_cycle  (Add_10000000,Data_0101)

   call Read_cycle   (Add_00000000,Output_0101)
   call Write_cycle  (Add_00000000,Data_1010)
   call Read_cycle   (Add_00000001,Output_0101)
   call Write_cycle  (Add_00000001,Data_1010)
   call Read_cycle   (Add_00000010,Output_0101)
   call Write_cycle  (Add_00000010,Data_1010)
   call Read_cycle   (Add_00000100,Output_0101)
   call Write_cycle  (Add_00000100,Data_1010)
   call Read_cycle   (Add_00001000,Output_0101)
   call Write_cycle  (Add_00001000,Data_1010)
   call Read_cycle   (Add_00010000,Output_0101)
   call Write_cycle  (Add_00010000,Data_1010)
   call Read_cycle   (Add_00100000,Output_0101)
   call Write_cycle  (Add_00100000,Data_1010)
   call Read_cycle   (Add_01000000,Output_0101)
   call Write_cycle  (Add_01000000,Data_1010)
   call Read_cycle   (Add_10000000,Output_0101)
   call Write_cycle  (Add_10000000,Data_1010)

   call Read_cycle   (Add_00000000,Data_1010)
   call Read_cycle   (Add_00000001,Data_1010)
   call Read_cycle   (Add_00000010,Data_1010)
   call Read_cycle   (Add_00000100,Data_1010)
   call Read_cycle   (Add_00001000,Data_1010)
   call Read_cycle   (Add_00010000,Data_1010)
   call Read_cycle   (Add_00100000,Data_1010)
   call Read_cycle   (Add_01000000,Data_1010)
   call Read_cycle   (Add_10000000,Data_1010)

end unit


unit "unit2, test Chip Select 1 Bar"
   execute Initialize
   call Write_cycle (Add_00000000,Data_0000)
   call Read_cycle  (Add_00000000,Output_0000)
   execute CS1bar_false
   execute  Add_00000000
   execute  Data_1111_CS1bar_false
   execute  End_cycle
   execute CS1bar_true
   call Read_cycle  (Add_00000000,Output_0000)
end unit

unit "unit3, test Chip Select 2"
   execute Initialize
   call Write_cycle (Add_00000000,Data_0000)
   call Read_cycle  (Add_00000000,Output_0000)
   execute CS2_false
   execute  Add_00000000
   execute  Data_1111_CS2_false
   execute  End_cycle
   execute CS2_true
   call Read_cycle  (Add_00000000,Output_0000)
end unit

unit "unit 4, test Output Enable Bar"
   execute Initialize
   call Write_cycle  (Add_00000000,Data_0000)
   call Read_cycle   (Add_00000000,Output_0000)
   execute OEbar_false
   call Write_cycle  (Add_00000000,Data_0000)
   call Read_cycle   (Add_00000000,Output_ZZZZ)
end unit


!End of test