!!!!    6    0    1  987185838  V718a                                         

! Device           : idt7132
! Function         : 2k X 8 static RAM with Dual Ports
! revision         : B.01.00
! safeguard        : high_out_hcmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

!warning "pullups will be needed to test open collector outputs pins 3 & 49"
!warning "pullups will be needed to test high impedance outputs pins 17 to 20"
!warning "pullups will be needed to test high impedance outputs pins 27 to 30"
warning "PIN OUT for 52 pin LCC/PLCC package"

vector cycle 1000n
receive delay 900n

assign  VCC               to pins  52
assign  GND               to pins  26

assign  Addr_R            to pins  47,36,37,38,39,40,41,42,43,44,45
assign  IO_R              to pins  34,33,32,31,30,29,28,27
assign  IO_R_D0           to pins  27   !AT Added for minimum pin test.
assign  IO_R_D1           to pins  28   !AT Added for minimum pin test.
assign  IO_R_D2           to pins  29   !AT Added for minimum pin test.
assign  IO_R_D3           to pins  30   !AT Added for minimum pin test.
assign  IO_R_D4           to pins  31   !AT Added for minimum pin test.
assign  IO_R_D5           to pins  32   !AT Added for minimum pin test.
assign  IO_R_D6           to pins  33   !AT Added for minimum pin test.
assign  IO_R_D7           to pins  34   !AT Added for minimum pin test.

assign  OE_bar_R          to pins  46
assign  CE_bar_R          to pins  51
assign  RW_R              to pins  50
assign  Busy_bar_R        to pins  49

assign  Addr_L            to pins  5,16,15,14,13,12,11,10,9,8,7
assign  IO_L              to pins  24,23,22,21,20,19,18,17
assign  IO_L_D0           to pins  17   !AT Added for minimum pin test.
assign  IO_L_D1           to pins  18   !AT Added for minimum pin test.
assign  IO_L_D2           to pins  19   !AT Added for minimum pin test.
assign  IO_L_D3           to pins  20   !AT Added for minimum pin test.
assign  IO_L_D4           to pins  21   !AT Added for minimum pin test.
assign  IO_L_D5           to pins  22   !AT Added for minimum pin test.
assign  IO_L_D6           to pins  23   !AT Added for minimum pin test.
assign  IO_L_D7           to pins  24   !AT Added for minimum pin test.

assign  OE_bar_L          to pins   6
assign  CE_bar_L          to pins   1
assign  RW_L              to pins   2
assign  Busy_bar_L        to pins   3

assign  No_Connects       to pins   4,25,35,48

family  TTL

power   VCC, GND

inputs      Addr_R, OE_bar_R, CE_bar_R, RW_R
inputs      Addr_L, OE_bar_L, CE_bar_L, RW_L

outputs     Busy_bar_R, Busy_bar_L

bidirectional IO_R, IO_L
bidirectional IO_R_D0, IO_R_D1, IO_R_D2, IO_R_D3 !AT Added for min. pin test.
bidirectional IO_R_D4, IO_R_D5, IO_R_D6, IO_R_D7 !AT Added for min. pin test.
bidirectional IO_L_D0, IO_L_D1, IO_L_D2, IO_L_D3 !AT Added for min. pin test.
bidirectional IO_L_D4, IO_L_D5, IO_L_D6, IO_L_D7 !AT Added for min. pin test.

nondigital   No_Connects

format hexadecimal IO_R, IO_L

disable  IO_R            with   OE_bar_R  to "1"
disable  IO_R            with   CE_bar_R  to "1"
disable  IO_L            with   OE_bar_L  to "1"
disable  IO_L            with   CE_bar_L  to "1"

when RW_R  is "0"  inputs IO_R
when RW_R  is "1"  outputs IO_R
when RW_L  is "0"  inputs IO_L
when RW_L  is "1"  outputs IO_L
when OE_bar_R is "1" inactive IO_R
when CE_bar_R is "1" inactive IO_R
when OE_bar_L is "1" inactive IO_L
when CE_bar_L is "1" inactive IO_L

trace IO_R to Addr_R, OE_bar_R, CE_bar_R, RW_R
trace IO_L to Addr_L, OE_bar_L, CE_bar_L, RW_L
trace Busy_bar_L, Busy_bar_R to Addr_R, OE_bar_R, CE_bar_R, RW_R
trace Busy_bar_L, Busy_bar_R to Addr_L, OE_bar_L, CE_bar_L, RW_L

set load on pins  3,49         to pull up
set load on pins  17,18,19,20  to pull up
set load on pins  27,28,29,30  to pull up

!*****************************************************************
!*****************************************************************

vector   Set_up_Right
   set   Addr_R      to "00000000000"
   set   RW_R        to "1"
   set   OE_bar_R    to "0"
   set   CE_bar_R    to "0"
   set   CE_bar_L    to "1"
end vector

vector   Set_up_Left
   set   Addr_L      to "00000000000"
   set   RW_L        to "1"
   set   OE_bar_L    to "0"
   set   CE_bar_L    to "0"
   set   CE_bar_R    to "1"
end vector

vector   Keep_inputs_left
   set   Addr_L      to "kkkkkkkkkkk"
   set   RW_L        to "k"
   set   OE_bar_L    to "k"
   set   CE_bar_L    to "k"
   set   CE_bar_R    to "k"
end vector

vector   Keep_inputs_right
   set   Addr_R      to "kkkkkkkkkkk"
   set   RW_R        to "k"
   set   OE_bar_R    to "k"
   set   CE_bar_R    to "k"
   set   CE_bar_L    to "k"
end vector

vector   Write_Right_True
   initialize        to Keep_inputs_right
   drive IO_R
   set   IO_R        to "kk"
   set   RW_R        to "0"
end vector

vector   Busy_Right_False
   initialize        to Keep_inputs_left
   set   Busy_bar_R  to "1"
end vector

vector   Busy_Right_True
   initialize        to Keep_inputs_left
   set   Addr_R      to "00000000000"
   set   CE_bar_R    to "0"
   set   Busy_bar_R  to "0"
end vector

vector   CE_Right_True
   initialize        to Keep_inputs_right
   set   CE_bar_R    to "0"
end vector

vector   CE_Right_False
   initialize        to Keep_inputs_right
   set   CE_bar_R    to "1"
end vector

vector   OE_Right_False
   initialize        to Keep_inputs_right
   set   OE_bar_R    to "1"
end vector

vector   End_write_cycle_Right
   initialize        to Keep_inputs_right
   drive IO_R
   set   IO_R        to "KK"
   set   RW_R        to "1"
end vector

vector   Write_Left_True
   initialize        to Keep_inputs_left
   drive IO_L
   set   IO_L        to "kk"
   set   RW_L        to "0"
end vector

vector   Busy_Left_False
   initialize        to Keep_inputs_right
   set   Busy_bar_L  to "1"
end vector

vector   Busy_Left_True
   initialize        to Keep_inputs_right
   set   Addr_L      to "00000000000"
   set   CE_bar_L    to "0"
   set   Busy_bar_L  to "0"
end vector

vector   CE_Left_True
   initialize        to Keep_inputs_left
   set   CE_bar_L    to "0"
end vector

vector   CE_Left_False
   initialize        to Keep_inputs_left
   set   CE_bar_L    to "1"
end vector

vector   OE_Left_False
   initialize        to Keep_inputs_left
   set   OE_bar_L    to "1"
end vector

vector   End_write_cycle_Left
   initialize        to Keep_inputs_left
   drive IO_L
   set   IO_L        to "KK"
   set   RW_L        to "1"
end vector

!------------------------------------------ Address Vectors
vector   Address_R_00000000000
   initialize        to Keep_inputs_right
   set   Addr_R      to "00000000000"
end vector

vector   Address_R_00000000001
   initialize        to Keep_inputs_right
   set   Addr_R      to "00000000001"
end vector

vector   Address_R_00000000010
   initialize        to Keep_inputs_right
   set   Addr_R      to "00000000010"
end vector

vector   Address_R_00000000100
   initialize        to Keep_inputs_right
   set   Addr_R      to "00000000100"
end vector

vector   Address_R_00000001000
   initialize        to Keep_inputs_right
   set   Addr_R      to "00000001000"
end vector

vector   Address_R_00000010000
   initialize        to Keep_inputs_right
   set   Addr_R      to "00000010000"
end vector

vector   Address_R_00000100000
   initialize        to Keep_inputs_right
   set   Addr_R      to "00000100000"
end vector

vector   Address_R_00001000000
   initialize        to Keep_inputs_right
   set   Addr_R      to "00001000000"
end vector

vector   Address_R_00010000000
   initialize        to Keep_inputs_right
   set   Addr_R      to "00010000000"
end vector

vector   Address_R_00100000000
   initialize        to Keep_inputs_right
   set   Addr_R      to "00100000000"
end vector

vector   Address_R_01000000000
   initialize        to Keep_inputs_right
   set   Addr_R      to "01000000000"
end vector

vector   Address_R_10000000000
   initialize        to Keep_inputs_right
   set   Addr_R      to "10000000000"
end vector

vector   Address_L_11111111111
   initialize        to Keep_inputs_left
   set   Addr_L      to "11111111111"
end vector

vector   Address_L_11111111110
   initialize        to Keep_inputs_left
   set   Addr_L      to "11111111110"
end vector

vector   Address_L_11111111101
   initialize        to Keep_inputs_left
   set   Addr_L      to "11111111101"
end vector

vector   Address_L_11111111011
   initialize        to Keep_inputs_left
   set   Addr_L      to "11111111011"
end vector

vector   Address_L_11111110111
   initialize        to Keep_inputs_left
   set   Addr_L      to "11111110111"
end vector

vector   Address_L_11111101111
   initialize        to Keep_inputs_left
   set   Addr_L      to "11111101111"
end vector

vector   Address_L_11111011111
   initialize        to Keep_inputs_left
   set   Addr_L      to "11111011111"
end vector

vector   Address_L_11110111111
   initialize        to Keep_inputs_left
   set   Addr_L      to "11110111111"
end vector

vector   Address_L_11101111111
   initialize        to Keep_inputs_left
   set   Addr_L      to "11101111111"
end vector

vector   Address_L_11011111111
   initialize        to Keep_inputs_left
   set   Addr_L      to "11011111111"
end vector

vector   Address_L_10111111111
   initialize        to Keep_inputs_left
   set   Addr_L      to "10111111111"
end vector

vector   Address_L_01111111111
   initialize        to Keep_inputs_left
   set   Addr_L      to "01111111111"
end vector


!------------------------------------------ Data Vectors

vector   Data_R_55_drive
   initialize        to Keep_inputs_right
   drive IO_R
   set   IO_R        to "55"
end vector

vector   Data_R_55_rcv
   initialize        to Keep_inputs_right
   receive IO_R
   set   IO_R        to "55"
end vector

vector   Data_R_AA_drive
   initialize        to Keep_inputs_right
   drive IO_R
   set   IO_R        to "AA"
end vector

vector   Data_R_AA_rcv
   initialize        to Keep_inputs_right
   receive IO_R
   set   IO_R        to "AA"
end vector

vector   Data_R_XF_rcv
   initialize        to Keep_inputs_right
   receive IO_R
   set   IO_R        to "XF"
end vector

vector   Data_L_55_drive
   initialize        to Keep_inputs_left
   drive IO_L
   set   IO_L        to "55"
end vector

vector   Data_L_55_rcv
   initialize        to Keep_inputs_left
   receive IO_L
   set   IO_L        to "55"
end vector

vector   Data_L_AA_drive
   initialize        to Keep_inputs_left
   drive IO_L
   set   IO_L        to "AA"
end vector

vector   Data_L_AA_rcv
   initialize        to Keep_inputs_left
   receive IO_L
   set   IO_L        to "AA"
end vector

vector   Data_L_XF_rcv
   initialize        to Keep_inputs_left
   receive IO_L
   set   IO_L        to "XF"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   W_R_lo_IO_R_D0
   initialize        to Keep_inputs_right
   drive IO_R_D0
   set   IO_R_D0     to "k"
   set   RW_R        to "0"
end vector

vector   W_R_hi_IO_R_D0
   initialize        to Keep_inputs_right
   drive IO_R_D0
   set   IO_R_D0     to "k"
   set   RW_R        to "1"
end vector

vector   W_L_lo_IO_L_D0
   initialize        to Keep_inputs_left
   drive IO_L_D0
   set   IO_L_D0     to "k"
   set   RW_L        to "0"
end vector

vector   W_L_hi_IO_L_D0
   initialize        to Keep_inputs_left
   drive IO_L_D0
   set   IO_L_D0     to "k"
   set   RW_L        to "1"
end vector

vector   Data_R_D0_0_drive
   initialize        to Keep_inputs_right
   drive IO_R_D0
   set   IO_R_D0     to "0"
end vector

vector   Data_R_D0_1_drive
   initialize        to Keep_inputs_right
   drive IO_R_D0
   set   IO_R_D0     to "1"
end vector

vector   Data_R_D0_0_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D0
   set     IO_R_D0   to "0"
end vector

vector   Data_R_D0_1_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D0
   set     IO_R_D0   to "1"
end vector

vector   Data_L_D0_0_drive
   initialize        to Keep_inputs_left
   drive IO_L_D0
   set   IO_L_D0     to "0"
end vector

vector   Data_L_D0_1_drive
   initialize        to Keep_inputs_left
   drive IO_L_D0
   set   IO_L_D0     to "1"
end vector

vector   Data_L_D0_0_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D0
   set     IO_L_D0   to "0"
end vector

vector   Data_L_D0_1_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D0
   set     IO_L_D0   to "1"
end vector

vector   W_R_lo_IO_R_D1
   initialize        to Keep_inputs_right
   drive IO_R_D1
   set   IO_R_D1     to "k"
   set   RW_R        to "0"
end vector

vector   W_R_hi_IO_R_D1
   initialize        to Keep_inputs_right
   drive IO_R_D1
   set   IO_R_D1     to "k"
   set   RW_R        to "1"
end vector

vector   W_L_lo_IO_L_D1
   initialize        to Keep_inputs_left
   drive IO_L_D1
   set   IO_L_D1     to "k"
   set   RW_L        to "0"
end vector

vector   W_L_hi_IO_L_D1
   initialize        to Keep_inputs_left
   drive IO_L_D1
   set   IO_L_D1     to "k"
   set   RW_L        to "1"
end vector

vector   Data_R_D1_0_drive
   initialize        to Keep_inputs_right
   drive IO_R_D1
   set   IO_R_D1     to "0"
end vector

vector   Data_R_D1_1_drive
   initialize        to Keep_inputs_right
   drive IO_R_D1
   set   IO_R_D1     to "1"
end vector

vector   Data_R_D1_0_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D1
   set     IO_R_D1   to "0"
end vector

vector   Data_R_D1_1_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D1
   set     IO_R_D1   to "1"
end vector

vector   Data_L_D1_0_drive
   initialize        to Keep_inputs_left
   drive IO_L_D1
   set   IO_L_D1     to "0"
end vector

vector   Data_L_D1_1_drive
   initialize        to Keep_inputs_left
   drive IO_L_D1
   set   IO_L_D1     to "1"
end vector

vector   Data_L_D1_0_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D1
   set     IO_L_D1   to "0"
end vector

vector   Data_L_D1_1_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D1
   set     IO_L_D1   to "1"
end vector

vector   W_R_lo_IO_R_D2
   initialize        to Keep_inputs_right
   drive IO_R_D2
   set   IO_R_D2     to "k"
   set   RW_R        to "0"
end vector

vector   W_R_hi_IO_R_D2
   initialize        to Keep_inputs_right
   drive IO_R_D2
   set   IO_R_D2     to "k"
   set   RW_R        to "1"
end vector

vector   W_L_lo_IO_L_D2
   initialize        to Keep_inputs_left
   drive IO_L_D2
   set   IO_L_D2     to "k"
   set   RW_L        to "0"
end vector

vector   W_L_hi_IO_L_D2
   initialize        to Keep_inputs_left
   drive IO_L_D2
   set   IO_L_D2     to "k"
   set   RW_L        to "1"
end vector

vector   Data_R_D2_0_drive
   initialize        to Keep_inputs_right
   drive IO_R_D2
   set   IO_R_D2     to "0"
end vector

vector   Data_R_D2_1_drive
   initialize        to Keep_inputs_right
   drive IO_R_D2
   set   IO_R_D2     to "1"
end vector

vector   Data_R_D2_0_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D2
   set     IO_R_D2   to "0"
end vector

vector   Data_R_D2_1_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D2
   set     IO_R_D2   to "1"
end vector

vector   Data_L_D2_0_drive
   initialize        to Keep_inputs_left
   drive IO_L_D2
   set   IO_L_D2     to "0"
end vector

vector   Data_L_D2_1_drive
   initialize        to Keep_inputs_left
   drive IO_L_D2
   set   IO_L_D2     to "1"
end vector

vector   Data_L_D2_0_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D2
   set     IO_L_D2   to "0"
end vector

vector   Data_L_D2_1_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D2
   set     IO_L_D2   to "1"
end vector

vector   W_R_lo_IO_R_D3
   initialize        to Keep_inputs_right
   drive IO_R_D3
   set   IO_R_D3     to "k"
   set   RW_R        to "0"
end vector

vector   W_R_hi_IO_R_D3
   initialize        to Keep_inputs_right
   drive IO_R_D3
   set   IO_R_D3     to "k"
   set   RW_R        to "1"
end vector

vector   W_L_lo_IO_L_D3
   initialize        to Keep_inputs_left
   drive IO_L_D3
   set   IO_L_D3     to "k"
   set   RW_L        to "0"
end vector

vector   W_L_hi_IO_L_D3
   initialize        to Keep_inputs_left
   drive IO_L_D3
   set   IO_L_D3     to "k"
   set   RW_L        to "1"
end vector

vector   Data_R_D3_0_drive
   initialize        to Keep_inputs_right
   drive IO_R_D3
   set   IO_R_D3     to "0"
end vector

vector   Data_R_D3_1_drive
   initialize        to Keep_inputs_right
   drive IO_R_D3
   set   IO_R_D3     to "1"
end vector

vector   Data_R_D3_0_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D3
   set     IO_R_D3   to "0"
end vector

vector   Data_R_D3_1_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D3
   set     IO_R_D3   to "1"
end vector

vector   Data_L_D3_0_drive
   initialize        to Keep_inputs_left
   drive IO_L_D3
   set   IO_L_D3     to "0"
end vector

vector   Data_L_D3_1_drive
   initialize        to Keep_inputs_left
   drive IO_L_D3
   set   IO_L_D3     to "1"
end vector

vector   Data_L_D3_0_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D3
   set     IO_L_D3   to "0"
end vector

vector   Data_L_D3_1_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D3
   set     IO_L_D3   to "1"
end vector

vector   W_R_lo_IO_R_D4
   initialize        to Keep_inputs_right
   drive IO_R_D4
   set   IO_R_D4     to "k"
   set   RW_R        to "0"
end vector

vector   W_R_hi_IO_R_D4
   initialize        to Keep_inputs_right
   drive IO_R_D4
   set   IO_R_D4     to "k"
   set   RW_R        to "1"
end vector

vector   W_L_lo_IO_L_D4
   initialize        to Keep_inputs_left
   drive IO_L_D4
   set   IO_L_D4     to "k"
   set   RW_L        to "0"
end vector

vector   W_L_hi_IO_L_D4
   initialize        to Keep_inputs_left
   drive IO_L_D4
   set   IO_L_D4     to "k"
   set   RW_L        to "1"
end vector

vector   Data_R_D4_0_drive
   initialize        to Keep_inputs_right
   drive IO_R_D4
   set   IO_R_D4     to "0"
end vector

vector   Data_R_D4_1_drive
   initialize        to Keep_inputs_right
   drive IO_R_D4
   set   IO_R_D4     to "1"
end vector

vector   Data_R_D4_0_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D4
   set     IO_R_D4   to "0"
end vector

vector   Data_R_D4_1_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D4
   set     IO_R_D4   to "1"
end vector

vector   Data_L_D4_0_drive
   initialize        to Keep_inputs_left
   drive IO_L_D4
   set   IO_L_D4     to "0"
end vector

vector   Data_L_D4_1_drive
   initialize        to Keep_inputs_left
   drive IO_L_D4
   set   IO_L_D4     to "1"
end vector

vector   Data_L_D4_0_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D4
   set     IO_L_D4   to "0"
end vector

vector   Data_L_D4_1_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D4
   set     IO_L_D4   to "1"
end vector

vector   W_R_lo_IO_R_D5
   initialize        to Keep_inputs_right
   drive IO_R_D5
   set   IO_R_D5     to "k"
   set   RW_R        to "0"
end vector

vector   W_R_hi_IO_R_D5
   initialize        to Keep_inputs_right
   drive IO_R_D5
   set   IO_R_D5     to "k"
   set   RW_R        to "1"
end vector

vector   W_L_lo_IO_L_D5
   initialize        to Keep_inputs_left
   drive IO_L_D5
   set   IO_L_D5     to "k"
   set   RW_L        to "0"
end vector

vector   W_L_hi_IO_L_D5
   initialize        to Keep_inputs_left
   drive IO_L_D5
   set   IO_L_D5     to "k"
   set   RW_L        to "1"
end vector

vector   Data_R_D5_0_drive
   initialize        to Keep_inputs_right
   drive IO_R_D5
   set   IO_R_D5     to "0"
end vector

vector   Data_R_D5_1_drive
   initialize        to Keep_inputs_right
   drive IO_R_D5
   set   IO_R_D5     to "1"
end vector

vector   Data_R_D5_0_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D5
   set     IO_R_D5   to "0"
end vector

vector   Data_R_D5_1_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D5
   set     IO_R_D5   to "1"
end vector

vector   Data_L_D5_0_drive
   initialize        to Keep_inputs_left
   drive IO_L_D5
   set   IO_L_D5     to "0"
end vector

vector   Data_L_D5_1_drive
   initialize        to Keep_inputs_left
   drive IO_L_D5
   set   IO_L_D5     to "1"
end vector

vector   Data_L_D5_0_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D5
   set     IO_L_D5   to "0"
end vector

vector   Data_L_D5_1_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D5
   set     IO_L_D5   to "1"
end vector

vector   W_R_lo_IO_R_D6
   initialize        to Keep_inputs_right
   drive IO_R_D6
   set   IO_R_D6     to "k"
   set   RW_R        to "0"
end vector

vector   W_R_hi_IO_R_D6
   initialize        to Keep_inputs_right
   drive IO_R_D6
   set   IO_R_D6     to "k"
   set   RW_R        to "1"
end vector

vector   W_L_lo_IO_L_D6
   initialize        to Keep_inputs_left
   drive IO_L_D6
   set   IO_L_D6     to "k"
   set   RW_L        to "0"
end vector

vector   W_L_hi_IO_L_D6
   initialize        to Keep_inputs_left
   drive IO_L_D6
   set   IO_L_D6     to "k"
   set   RW_L        to "1"
end vector

vector   Data_R_D6_0_drive
   initialize        to Keep_inputs_right
   drive IO_R_D6
   set   IO_R_D6     to "0"
end vector

vector   Data_R_D6_1_drive
   initialize        to Keep_inputs_right
   drive IO_R_D6
   set   IO_R_D6     to "1"
end vector

vector   Data_R_D6_0_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D6
   set     IO_R_D6   to "0"
end vector

vector   Data_R_D6_1_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D6
   set     IO_R_D6   to "1"
end vector

vector   Data_L_D6_0_drive
   initialize        to Keep_inputs_left
   drive IO_L_D6
   set   IO_L_D6     to "0"
end vector

vector   Data_L_D6_1_drive
   initialize        to Keep_inputs_left
   drive IO_L_D6
   set   IO_L_D6     to "1"
end vector

vector   Data_L_D6_0_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D6
   set     IO_L_D6   to "0"
end vector

vector   Data_L_D6_1_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D6
   set     IO_L_D6   to "1"
end vector

vector   W_R_lo_IO_R_D7
   initialize        to Keep_inputs_right
   drive IO_R_D7
   set   IO_R_D7     to "k"
   set   RW_R        to "0"
end vector

vector   W_R_hi_IO_R_D7
   initialize        to Keep_inputs_right
   drive IO_R_D7
   set   IO_R_D7     to "k"
   set   RW_R        to "1"
end vector

vector   W_L_lo_IO_L_D7
   initialize        to Keep_inputs_left
   drive IO_L_D7
   set   IO_L_D7     to "k"
   set   RW_L        to "0"
end vector

vector   W_L_hi_IO_L_D7
   initialize        to Keep_inputs_left
   drive IO_L_D7
   set   IO_L_D7     to "k"
   set   RW_L        to "1"
end vector

vector   Data_R_D7_0_drive
   initialize        to Keep_inputs_right
   drive IO_R_D7
   set   IO_R_D7     to "0"
end vector

vector   Data_R_D7_1_drive
   initialize        to Keep_inputs_right
   drive IO_R_D7
   set   IO_R_D7     to "1"
end vector

vector   Data_R_D7_0_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D7
   set     IO_R_D7   to "0"
end vector

vector   Data_R_D7_1_rcv
   initialize        to Keep_inputs_right
   receive IO_R_D7
   set     IO_R_D7   to "1"
end vector

vector   Data_L_D7_0_drive
   initialize        to Keep_inputs_left
   drive IO_L_D7
   set   IO_L_D7     to "0"
end vector

vector   Data_L_D7_1_drive
   initialize        to Keep_inputs_left
   drive IO_L_D7
   set   IO_L_D7     to "1"
end vector

vector   Data_L_D7_0_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D7
   set     IO_L_D7   to "0"
end vector

vector   Data_L_D7_1_rcv
   initialize        to Keep_inputs_left
   receive IO_L_D7
   set     IO_L_D7   to "1"
end vector


!***************************************************************
!*******************  subroutine section  **********************
!***************************************************************

sub Read_cycle_Right (Address, Data_Out)
   execute Address
   execute Data_Out
end sub

sub Write_cycle_Right (Address, Data_In)
   execute Address
   execute Data_In
   execute Write_Right_true
   execute End_write_cycle_Right
end sub

sub Read_cycle_Left (Address, Data_Out)
   execute Address
   execute Data_Out
end sub

sub Write_cycle_Left (Address, Data_In)
   execute Address
   execute Data_In
   execute Write_Left_true
   execute End_write_cycle_Left
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_Cycle" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_Cycle" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (data). This reference can be modified in the
!AT call statement.

sub Write_cycle_Right_Dx (Address, Data_In_Dx, W_R_lo_IO_R_Dx, W_R_hi_IO_R_Dx)
   execute Address
   execute Data_In_Dx
   execute W_R_lo_IO_R_Dx
   execute W_R_hi_IO_R_Dx
end sub

sub Write_cycle_Left_Dx (Address, Data_In_Dx, W_L_lo_IO_L_Dx, W_L_hi_IO_L_Dx)
   execute Address
   execute Data_In_Dx
   execute W_L_lo_IO_L_Dx
   execute W_L_hi_IO_L_Dx
end sub

!****************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest Left D0 Test"

   execute Set_Up_Left

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D0_0_drive, W_L_lo_IO_L_D0, W_L_hi_IO_L_D0)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D0_0_rcv)

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D0_1_drive, W_L_lo_IO_L_D0, W_L_hi_IO_L_D0)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D0_1_rcv)

end unit

unit   "awaretest Left D1 Test"

   execute Set_Up_Left

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D1_0_drive, W_L_lo_IO_L_D1, W_L_hi_IO_L_D1)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D1_0_rcv)

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D1_1_drive, W_L_lo_IO_L_D1, W_L_hi_IO_L_D1)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D1_1_rcv)

end unit

unit   "awaretest Left D2 Test"

   execute Set_Up_Left

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D2_0_drive, W_L_lo_IO_L_D2, W_L_hi_IO_L_D2)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D2_0_rcv)

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D2_1_drive, W_L_lo_IO_L_D2, W_L_hi_IO_L_D2)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D2_1_rcv)

end unit

unit   "awaretest Left D3 Test"

   execute Set_Up_Left

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D3_0_drive, W_L_lo_IO_L_D3, W_L_hi_IO_L_D3)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D3_0_rcv)

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D3_1_drive, W_L_lo_IO_L_D3, W_L_hi_IO_L_D3)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D3_1_rcv)

end unit

unit   "awaretest Left D4 Test"

   execute Set_Up_Left

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D4_0_drive, W_L_lo_IO_L_D4, W_L_hi_IO_L_D4)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D4_0_rcv)

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D4_1_drive, W_L_lo_IO_L_D4, W_L_hi_IO_L_D4)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D4_1_rcv)

end unit

unit   "awaretest Left D5 Test"

   execute Set_Up_Left

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D5_0_drive, W_L_lo_IO_L_D5, W_L_hi_IO_L_D5)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D5_0_rcv)

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D5_1_drive, W_L_lo_IO_L_D5, W_L_hi_IO_L_D5)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D5_1_rcv)

end unit

unit   "awaretest Left D6 Test"

   execute Set_Up_Left

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D6_0_drive, W_L_lo_IO_L_D6, W_L_hi_IO_L_D6)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D6_0_rcv)

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D6_1_drive, W_L_lo_IO_L_D6, W_L_hi_IO_L_D6)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D6_1_rcv)

end unit

unit   "awaretest Left D7 Test"

   execute Set_Up_Left

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D7_0_drive, W_L_lo_IO_L_D7, W_L_hi_IO_L_D7)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D7_0_rcv)

   call Write_cycle_Left_Dx (Address_L_11111111111, Data_L_D7_1_drive, W_L_lo_IO_L_D7, W_L_hi_IO_L_D7)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_D7_1_rcv)

end unit

unit   "awaretest Right D0 Test"

   execute Set_Up_Right

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D0_0_drive, W_R_lo_IO_R_D0, W_R_hi_IO_R_D0)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D0_0_rcv)

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D0_1_drive, W_R_lo_IO_R_D0, W_R_hi_IO_R_D0)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D0_1_rcv)

end unit

unit   "awaretest Right D1 Test"

   execute Set_Up_Right

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D1_0_drive, W_R_lo_IO_R_D1, W_R_hi_IO_R_D1)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D1_0_rcv)

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D1_1_drive, W_R_lo_IO_R_D1, W_R_hi_IO_R_D1)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D1_1_rcv)

end unit

unit   "awaretest Right D2 Test"

   execute Set_Up_Right

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D2_0_drive, W_R_lo_IO_R_D2, W_R_hi_IO_R_D2)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D2_0_rcv)

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D2_1_drive, W_R_lo_IO_R_D2, W_R_hi_IO_R_D2)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D2_1_rcv)

end unit

unit   "awaretest Right D3 Test"

   execute Set_Up_Right

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D3_0_drive, W_R_lo_IO_R_D3, W_R_hi_IO_R_D3)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D3_0_rcv)

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D3_1_drive, W_R_lo_IO_R_D3, W_R_hi_IO_R_D3)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D3_1_rcv)

end unit

unit   "awaretest Right D4 Test"

   execute Set_Up_Right

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D4_0_drive, W_R_lo_IO_R_D4, W_R_hi_IO_R_D4)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D4_0_rcv)

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D4_1_drive, W_R_lo_IO_R_D4, W_R_hi_IO_R_D4)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D4_1_rcv)

end unit

unit   "awaretest Right D5 Test"

   execute Set_Up_Right

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D5_0_drive, W_R_lo_IO_R_D5, W_R_hi_IO_R_D5)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D5_0_rcv)

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D5_1_drive, W_R_lo_IO_R_D5, W_R_hi_IO_R_D5)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D5_1_rcv)

end unit

unit   "awaretest Right D6 Test"

   execute Set_Up_Right

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D6_0_drive, W_R_lo_IO_R_D6, W_R_hi_IO_R_D6)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D6_0_rcv)

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D6_1_drive, W_R_lo_IO_R_D6, W_R_hi_IO_R_D6)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D6_1_rcv)

end unit

unit   "awaretest Right D7 Test"

   execute Set_Up_Right

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D7_0_drive, W_R_lo_IO_R_D7, W_R_hi_IO_R_D7)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D7_0_rcv)

   call Write_cycle_Right_Dx (Address_R_00000000000, Data_R_D7_1_drive, W_R_lo_IO_R_D7, W_R_hi_IO_R_D7)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_D7_1_rcv)

end unit

   ! TEST CONCEPT:
   ! Use a 'walking-one' to access several RAM addresses on Right side.
   ! Write a 55 to those addresses.
   ! Read each address and re-write an AA.
   !  Use a 'walking-zero' to access several RAM addresses on the Left side.
   !  Write an AA to those addresses.
   !  Read each address and re-write a 55.
   !   From the Left side read the AA's re-written via the Right side.
   !   From the Right side, read the 55's re-written via the Left side.
   ! Note that the walking ones and zeros traverse Row and Column address.

unit "Test Left RAM"
   execute Set_Up_Left
   call Write_cycle_Left (Address_L_11111111111, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11111111110, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11111111101, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11111111011, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11111110111, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11111101111, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11111011111, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11110111111, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11101111111, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_11011111111, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_10111111111, Data_L_AA_drive)
   call Write_cycle_Left (Address_L_01111111111, Data_L_AA_drive)

   call Read_cycle_Left  (Address_L_11111111111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11111111111, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11111111110, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11111111110, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11111111101, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11111111101, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11111111011, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11111111011, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11111110111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11111110111, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11111101111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11111101111, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11111011111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11111011111, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11110111111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11110111111, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11101111111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11101111111, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_11011111111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_11011111111, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_10111111111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_10111111111, Data_L_55_drive)

   call Read_cycle_Left  (Address_L_01111111111, Data_L_AA_rcv)
   call Write_cycle_Left (Address_L_01111111111, Data_L_55_drive)

   call Read_cycle_Left (Address_L_11111111111, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11111111110, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11111111101, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11111111011, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11111110111, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11111101111, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11111011111, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11110111111, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11101111111, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_11011111111, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_10111111111, Data_L_55_rcv)
   call Read_cycle_Left (Address_L_01111111111, Data_L_55_rcv)
end unit

unit  "Test Right RAM"
   execute Set_up_Right
   call Write_cycle_Right (Address_R_00000000000, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00000000001, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00000000010, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00000000100, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00000001000, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00000010000, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00000100000, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00001000000, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00010000000, Data_R_55_drive)
   call Write_cycle_Right (Address_R_00100000000, Data_R_55_drive)
   call Write_cycle_Right (Address_R_01000000000, Data_R_55_drive)
   call Write_cycle_Right (Address_R_10000000000, Data_R_55_drive)

   call Read_cycle_Right  (Address_R_00000000000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00000000000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00000000001, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00000000001, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00000000010, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00000000010, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00000000100, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00000000100, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00000001000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00000001000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00000010000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00000010000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00000100000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00000100000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00001000000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00001000000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00010000000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00010000000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00100000000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_00100000000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_01000000000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_01000000000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_10000000000, Data_R_55_rcv)
   call Write_cycle_Right (Address_R_10000000000, Data_R_AA_drive)

   call Read_cycle_Right  (Address_R_00000000000, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00000000001, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00000000010, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00000000100, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00000001000, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00000010000, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00000100000, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00001000000, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00010000000, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_00100000000, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_01000000000, Data_R_AA_rcv)
   call Read_cycle_Right  (Address_R_10000000000, Data_R_AA_rcv)
end   unit

unit "Test Left RAM Chip Select"
   execute Set_Up_Left
   call Write_cycle_Left (Address_L_11111111111, Data_L_AA_drive)

   execute CE_Left_False
   call Write_cycle_Left (Address_L_11111111111, Data_L_55_drive)
   execute CE_Left_True

   call Read_cycle_Left  (Address_L_11111111111, Data_L_AA_rcv)
end unit

unit "Test Right RAM Chip Select"
   execute Set_Up_Right
   call Write_cycle_Right (Address_R_00000000000, Data_R_AA_drive)

   execute CE_Right_False
   call Write_cycle_Right (Address_R_00000000000, Data_R_55_drive)
   execute CE_Right_True

   call Read_cycle_Right  (Address_R_00000000000, Data_R_AA_rcv)
end unit

unit "test BUSY"
   execute Set_Up_Right
   execute Busy_Left_False
   execute Busy_Left_True

   execute Set_Up_Left
   execute Busy_Right_False
   execute Busy_Right_True
end unit

unit "Test Left RAM OE"
   execute Set_Up_Left
   call Write_cycle_Left (Address_L_11111111111, Data_L_55_drive)
   call Read_cycle_Left  (Address_L_11111111111, Data_L_55_rcv)
   execute OE_Left_False
   homingloop 3 times
     execute Data_L_XF_rcv  exit if pass
   end homingloop
end unit

unit "Test Right RAM OE"
   execute Set_Up_Right
   call Write_cycle_Right (Address_R_00000000000, Data_R_55_drive)
   call Read_cycle_Right  (Address_R_00000000000, Data_R_55_rcv)
   execute OE_Right_False
   homingloop 3 times
      execute Data_R_XF_rcv exit if pass
   end homingloop
end unit

!End of test