!!!!    6    0    1  987034979  V6bb6                                         

! Device           : 4723
! Function         : Latch totem dual_4_bit_addressable
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 1u
receive delay 900n

assign VDD           to pins 16
assign VSS           to pins  8

assign E1_Data_Input to pins 3
assign E2_Data_Input to pins 13
assign Write_Disable to pins 14
assign Reset         to pins 15
assign Address       to pins 2,1

assign E1_Data_Outputs  to pins 7,6,5,4
assign E1_Data_Out_D0   to pins 4            !AT Added for minimum pin test.
assign E1_Data_Out_D1   to pins 5            !AT Added for minimum pin test.
assign E1_Data_Out_D2   to pins 6            !AT Added for minimum pin test.
assign E1_Data_Out_D3   to pins 7            !AT Added for minimum pin test.

assign E2_Data_Outputs  to pins 12,11,10,9
assign E2_Data_Out_D0   to pins 9            !AT Added for minimum pin test.
assign E2_Data_Out_D1   to pins 10           !AT Added for minimum pin test.
assign E2_Data_Out_D2   to pins 11           !AT Added for minimum pin test.
assign E2_Data_Out_D3   to pins 12           !AT Added for minimum pin test.

power  VDD, VSS
family  CMOS

inputs E1_Data_Input, E2_Data_Input, Write_Disable, Reset, Address
outputs E1_Data_Outputs, E2_Data_Outputs
outputs E1_Data_Out_D0, E1_Data_Out_D1     !AT Added for minimum pin test.
outputs E1_Data_Out_D2, E1_Data_Out_D3     !AT Added for minimum pin test.
outputs E2_Data_Out_D0, E2_Data_Out_D1     !AT Added for minimum pin test.
outputs E2_Data_Out_D2, E2_Data_Out_D3     !AT Added for minimum pin test.

trace E1_Data_Outputs to E1_Data_Input,Write_Disable, Reset, Address
trace E2_Data_Outputs to E2_Data_Input,Write_Disable, Reset, Address


!***********************************************************************
!***********************************************************************

vector Address_00
     set Reset       to "0"
     set Address     to "00"
end vector

vector Address_01
     set Reset       to "0"
     set Address     to "01"
end vector

vector Address_10
     set Reset       to "0"
     set Address     to "10"
end vector

vector Address_11
     set Reset       to "0"
     set Address     to "11"
end vector

vector  Enable_Writing
     set Reset       to "0"
     set Address     to "KK"
     set Write_Disable  to  "0"
end vector

vector  E1_Data_Input_0
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "0"
end vector

vector  E2_Data_Input_0
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "0"
end vector

vector  E1_Data_Input_1
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "1"
end vector

vector  E2_Data_Input_1
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "1"
end vector

vector  E1_Data_Output_XXX0
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "K"
     set E1_Data_Outputs  to "XXX0"
end vector

vector  E1_Data_Output_XXX1
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "K"
     set E1_Data_Outputs  to "XXX1"
end vector

vector  E1_Data_Output_XX0X
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "K"
     set E1_Data_Outputs  to "XX0X"
end vector

vector  E1_Data_Output_XX1X
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "K"
     set E1_Data_Outputs  to "XX1X"
end vector

vector  E1_Data_Output_X0XX
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "K"
     set E1_Data_Outputs  to "X0XX"
end vector

vector  E1_Data_Output_X1XX
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "K"
     set E1_Data_Outputs  to "X1XX"
end vector

vector  E1_Data_Output_0XXX
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "K"
     set E1_Data_Outputs  to "0XXX"
end vector

vector  E1_Data_Output_1XXX
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E1_Data_Input  to "K"
     set E1_Data_Outputs  to "1XXX"
end vector

vector  E2_Data_Output_XXX0
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "K"
     set E2_Data_Outputs  to "XXX0"
end vector

vector  E2_Data_Output_XXX1
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "K"
     set E2_Data_Outputs  to "XXX1"
end vector

vector  E2_Data_Output_XX0X
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "K"
     set E2_Data_Outputs  to "XX0X"
end vector

vector  E2_Data_Output_XX1X
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "K"
     set E2_Data_Outputs  to "XX1X"
end vector

vector  E2_Data_Output_X0XX
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "K"
     set E2_Data_Outputs  to "X0XX"
end vector

vector  E2_Data_Output_X1XX
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "K"
     set E2_Data_Outputs  to "X1XX"
end vector

vector  E2_Data_Output_0XXX
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "K"
     set E2_Data_Outputs  to "0XXX"
end vector

vector  E2_Data_Output_1XXX
     set Reset       to "K"
     set Address     to "KK"
     set Write_Disable  to "K"
     set E2_Data_Input  to "K"
     set E2_Data_Outputs  to "1XXX"
end vector

vector  E1_Latch_Data
     set Address     to "KK"
     set E1_Data_Input  to "K"
     set Reset       to "K"
     set Write_Disable  to "1"
end vector

vector  E2_Latch_Data
     set Address      to "KK"
     set E2_Data_Input  to "K"
     set Reset       to "K"
     set Write_Disable  to "1"
end vector

vector  Reset_Device
     set Reset       to "1"
     set Write_Disable  to "1"
     set E1_Data_Outputs  to "0000"
     set E2_Data_Outputs  to "0000"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  E1_Data_Output_D0_0
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E1_Data_Input       to "K"
     set E1_Data_Out_D0  to "0"
end vector

vector  E1_Data_Output_D0_1
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E1_Data_Input       to "K"
     set E1_Data_Out_D0  to "1"
end vector

vector  E1_Data_Output_D1_0
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E1_Data_Input       to "K"
     set E1_Data_Out_D1  to "0"
end vector

vector  E1_Data_Output_D1_1
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E1_Data_Input       to "K"
     set E1_Data_Out_D1  to "1"
end vector

vector  E1_Data_Output_D2_0
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E1_Data_Input       to "K"
     set E1_Data_Out_D2  to "0"
end vector

vector  E1_Data_Output_D2_1
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E1_Data_Input       to "K"
     set E1_Data_Out_D2  to "1"
end vector

vector  E1_Data_Output_D3_0
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E1_Data_Input       to "K"
     set E1_Data_Out_D3  to "0"
end vector

vector  E1_Data_Output_D3_1
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E1_Data_Input       to "K"
     set E1_Data_Out_D3  to "1"
end vector

vector  E2_Data_Output_D0_0
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E2_Data_Input       to "K"
     set E2_Data_Out_D0  to "0"
end vector

vector  E2_Data_Output_D0_1
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E2_Data_Input       to "K"
     set E2_Data_Out_D0  to "1"
end vector

vector  E2_Data_Output_D1_0
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E2_Data_Input       to "K"
     set E2_Data_Out_D1  to "0"
end vector

vector  E2_Data_Output_D1_1
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E2_Data_Input       to "K"
     set E2_Data_Out_D1  to "1"
end vector

vector  E2_Data_Output_D2_0
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E2_Data_Input       to "K"
     set E2_Data_Out_D2  to "0"
end vector

vector  E2_Data_Output_D2_1
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E2_Data_Input       to "K"
     set E2_Data_Out_D2  to "1"
end vector

vector  E2_Data_Output_D3_0
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E2_Data_Input       to "K"
     set E2_Data_Out_D3  to "0"
end vector

vector  E2_Data_Output_D3_1
     set Reset               to "K"
     set Address             to "KK"
     set Write_Disable       to "K"
     set E2_Data_Input       to "K"
     set E2_Data_Out_D3  to "1"
end vector

vector  Reset_Device_Dx
     set Reset       to "1"
     set Write_Disable  to "1"
end vector

!***********************************************************************
!***********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest Element 1, D0 Test"
     execute Address_00
     execute Enable_Writing
     execute E1_Data_Input_0
     execute E1_Data_Output_D0_0
     execute E1_Data_Input_1
     execute E1_Data_Output_D0_1
     execute Reset_Device_Dx
end unit

unit   "awaretest Element 1, D1 Test"
     execute Address_01
     execute Enable_Writing
     execute E1_Data_Input_0
     execute E1_Data_Output_D1_0
     execute E1_Data_Input_1
     execute E1_Data_Output_D1_1
     execute Reset_Device_Dx
end unit

unit   "awaretest Element 1, D2 Test"
     execute Address_10
     execute Enable_Writing
     execute E1_Data_Input_0
     execute E1_Data_Output_D2_0
     execute E1_Data_Input_1
     execute E1_Data_Output_D2_1
     execute Reset_Device_Dx
end unit

unit   "awaretest Element 1, D3 Test"
     execute Address_11
     execute Enable_Writing
     execute E1_Data_Input_0
     execute E1_Data_Output_D3_0
     execute E1_Data_Input_1
     execute E1_Data_Output_D3_1
     execute Reset_Device_Dx
end unit

unit   "awaretest Element 2, D0 Test"
     execute Address_00
     execute Enable_Writing
     execute E2_Data_Input_0
     execute E2_Data_Output_D0_0
     execute E2_Data_Input_1
     execute E2_Data_Output_D0_1
     execute Reset_Device_Dx
end unit

unit   "awaretest Element 2, D1 Test"
     execute Address_01
     execute Enable_Writing
     execute E2_Data_Input_0
     execute E2_Data_Output_D1_0
     execute E2_Data_Input_1
     execute E2_Data_Output_D1_1
     execute Reset_Device_Dx
end unit

unit   "awaretest Element 2, D2 Test"
     execute Address_10
     execute Enable_Writing
     execute E2_Data_Input_0
     execute E2_Data_Output_D2_0
     execute E2_Data_Input_1
     execute E2_Data_Output_D2_1
     execute Reset_Device_Dx
end unit

unit   "awaretest Element 2, D3 Test"
     execute Address_11
     execute Enable_Writing
     execute E2_Data_Input_0
     execute E2_Data_Output_D3_0
     execute E2_Data_Input_1
     execute E2_Data_Output_D3_1
     execute Reset_Device_Dx
end unit

unit "Element 1, latch 0 test"
     execute Address_00
     execute Enable_Writing
     execute E1_Data_Input_0
     execute E1_Data_Output_XXX0
     execute E1_Data_Input_1
     execute E1_Data_Output_XXX1
     execute E1_Latch_Data
     execute E1_Data_Input_0
     execute E1_Data_Output_XXX1
     execute Reset_Device
end unit

unit "Element 1, Latch 1 test"
     execute Address_01
     execute Enable_Writing
     execute E1_Data_Input_0
     execute E1_Data_Output_XX0X
     execute E1_Data_Input_1
     execute E1_Data_Output_XX1X
     execute E1_Latch_Data
     execute E1_Data_Input_0
     execute E1_Data_Output_XX1X
     execute Reset_Device
end unit

unit "Element 1, Latch 2 test"
     execute Address_10
     execute Enable_Writing
     execute E1_Data_Input_0
     execute E1_Data_Output_X0XX
     execute E1_Data_Input_1
     execute E1_Data_Output_X1XX
     execute E1_Latch_Data
     execute E1_Data_Input_0
     execute E1_Data_Output_X1XX
     execute Reset_Device
end unit

unit "Element 1, Latch 3 test"
     execute Address_11
     execute Enable_Writing
     execute E1_Data_Input_0
     execute E1_Data_Output_0XXX
     execute E1_Data_Input_1
     execute E1_Data_Output_1XXX
     execute E1_Latch_Data
     execute E1_Data_Input_0
     execute E1_Data_Output_1XXX
     execute Reset_Device
end unit

unit "Element 2, Latch 0 test"
     execute Address_00
     execute Enable_Writing
     execute E2_Data_Input_0
     execute E2_Data_Output_XXX0
     execute E2_Data_Input_1
     execute E2_Data_Output_XXX1
     execute E2_Latch_Data
     execute E2_Data_Input_0
     execute E2_Data_Output_XXX1
     execute Reset_Device
end unit

unit "Element 2, Latch 1 test"
     execute Address_01
     execute Enable_Writing
     execute E2_Data_Input_0
     execute E2_Data_Output_XX0X
     execute E2_Data_Input_1
     execute E2_Data_Output_XX1X
     execute E2_Latch_Data
     execute E2_Data_Input_0
     execute E2_Data_Output_XX1X
     execute Reset_Device
end unit

unit "Element 2, Latch 2 test"
     execute Address_10
     execute Enable_Writing
     execute E2_Data_Input_0
     execute E2_Data_Output_X0XX
     execute E2_Data_Input_1
     execute E2_Data_Output_X1XX
     execute E2_Latch_Data
     execute E2_Data_Input_0
     execute E2_Data_Output_X1XX
     execute Reset_Device
end unit

unit "Element 2, Latch 3 test"
     execute Address_11
     execute Enable_Writing
     execute E2_Data_Input_0
     execute E2_Data_Output_0XXX
     execute E2_Data_Input_1
     execute E2_Data_Output_1XXX
     execute E2_Latch_Data
     execute E2_Data_Input_0
     execute E2_Data_Output_1XXX
     execute Reset_Device
end unit


!    End of test