!!!!    6    0    1  986800857  V758f                                         

! Device           : 2168
! Function         : Static RAM 3-state 4k x 4
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

assign    VCC            to pins   20
assign    GND            to pins   10

assign    Address        to pins   16,17,18,19,1,2,3,4,8,7,6,5

assign    Data           to pins   12,13,14,15
assign    Data_D0        to pins   15   !AT Added for minimum pin test.
assign    Data_D1        to pins   14   !AT Added for minimum pin test.
assign    Data_D2        to pins   13   !AT Added for minimum pin test.
assign    Data_D3        to pins   12   !AT Added for minimum pin test.

assign    Write_enable_bar      to pins   11
assign    Chip_enable_bar       to pins   9

family    TTL

power     VCC, GND

inputs    Address, Write_enable_bar, Chip_enable_bar

bidirectional  Data
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.

when      Write_enable_bar    is    "0"   inputs   Data
when      Write_enable_bar    is    "1"   outputs  Data
when      Chip_enable_bar     is    "1"   inactive Data

trace     Data  to  Address, Write_enable_bar, Chip_enable_bar

disable   Data   with   Write_enable_bar     to   "0"
disable   Data   with   Chip_enable_bar      to   "1"

!***************************************************************
!***************************************************************

vector   Memory_disabled
     set  Chip_enable_bar     to  "1"
     set  Write_enable_bar    to  "1"
end vector

vector   Chip_enabled
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "0"
     set  Write_enable_bar    to  "k"
end vector

vector   Chip_enable_false
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "1"
     set  Write_enable_bar    to  "k"
end vector

vector   Write_enabled
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "k"
     set  Write_enable_bar    to  "0"
end vector

vector   Data_written
          drive  Data
     set  Data                to  "kkkk"
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "1"
     set  Write_enable_bar    to  "1"
end vector

vector   Output_valid
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "0"
     set  Write_enable_bar    to  "k"
end vector


vector   Address_000000000000
     initialize to Memory_disabled
     set  Address     to "000000000000"
end vector

vector   Address_000000000001
     initialize to Memory_disabled
     set  Address     to "000000000001"
end vector

vector   Address_000000000011
     initialize to Memory_disabled
     set  Address     to "000000000011"
end vector

vector   Address_000000000111
     initialize to Memory_disabled
     set  Address     to "000000000111"
end vector

vector   Address_000000001111
     initialize to Memory_disabled
     set  Address     to "000000001111"
end vector

vector   Address_000000011111
     initialize to Memory_disabled
     set  Address     to "000000011111"
end vector

vector   Address_000000111111
     initialize to Memory_disabled
     set  Address     to "000000111111"
end vector

vector   Address_000001111111
     initialize to Memory_disabled
     set  Address     to "000001111111"
end vector

vector   Address_000011111111
     initialize to Memory_disabled
     set  Address     to "000011111111"
end vector

vector   Address_000111111111
     initialize to Memory_disabled
     set  Address     to "000111111111"
end vector

vector   Address_001111111111
     initialize to Memory_disabled
     set  Address     to "001111111111"
end vector

vector   Address_011111111111
     initialize to Memory_disabled
     set  Address     to "011111111111"
end vector

vector   Address_111111111111
     initialize to Memory_disabled
     set  Address     to "111111111111"
end vector

vector   Data_In_0000
     initialize to Write_enabled
          drive  Data
     set  Data            to "0000"
end vector

vector   Data_In_0001
     initialize to Write_enabled
          drive  Data
     set  Data            to "0001"
end vector

vector   Data_In_0011
     initialize to Write_enabled
          drive  Data
     set  Data            to "0011"
end vector

vector   Data_In_0010
     initialize to Write_enabled
          drive  Data
     set  Data            to "0010"
end vector

vector   Data_In_0110
     initialize to Write_enabled
          drive  Data
     set  Data            to "0110"
end vector

vector   Data_In_0111
     initialize to Write_enabled
          drive  Data
     set  Data            to "0111"
end vector

vector   Data_In_0101
     initialize to Write_enabled
          drive  Data
     set  Data            to "0101"
end vector

vector   Data_In_0100
     initialize to Write_enabled
          drive  Data
     set  Data            to "0100"
end vector

vector   Data_In_1100
     initialize to Write_enabled
          drive  Data
     set  Data            to "1100"
end vector

vector   Data_In_1101
     initialize to Write_enabled
          drive  Data
     set  Data            to "1101"
end vector

vector   Data_In_1111
     initialize to Write_enabled
          drive  Data
     set  Data            to "1111"
end vector

vector   Data_In_1110
     initialize to Write_enabled
          drive  Data
     set  Data            to "1110"
end vector

vector   Data_In_1010
     initialize to Write_enabled
          drive  Data
     set  Data            to "1010"
end vector

vector   Read_Data_0000
     initialize to Output_valid
          receive  Data
     set  Data            to "0000"
end vector

vector   Read_Data_0001
     initialize to Output_valid
          receive  Data
     set  Data            to "0001"
end vector

vector   Read_Data_0011
     initialize to Output_valid
          receive  Data
     set  Data            to "0011"
end vector

vector   Read_Data_0010
     initialize to Output_valid
          receive  Data
     set  Data            to "0010"
end vector

vector   Read_Data_0110
     initialize to Output_valid
          receive  Data
     set  Data            to "0110"
end vector

vector   Read_Data_0111
     initialize to Output_valid
          receive  Data
     set  Data            to "0111"
end vector

vector   Read_Data_0101
     initialize to Output_valid
          receive  Data
     set  Data            to "0101"
end vector

vector   Read_Data_0100
     initialize to Output_valid
          receive  Data
     set  Data            to "0100"
end vector

vector   Read_Data_1100
     initialize to Output_valid
          receive  Data
     set  Data            to "1100"
end vector

vector   Read_Data_1101
     initialize to Output_valid
          receive  Data
     set  Data            to "1101"
end vector

vector   Read_Data_1111
     initialize to Output_valid
          receive  Data
     set  Data            to "1111"
end vector

vector   Read_Data_1110
     initialize to Output_valid
          receive  Data
     set  Data            to "1110"
end vector

vector   Read_Data_1010
     initialize to Output_valid
          receive  Data
     set  Data            to "1010"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Data_written_D0
          drive  Data_D0
     set  Data_D0             to  "k"
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "1"
     set  Write_enable_bar    to  "1"
end vector

vector   Data_written_D1
          drive  Data_D1
     set  Data_D1             to  "k"
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "1"
     set  Write_enable_bar    to  "1"
end vector

vector   Data_written_D2
          drive  Data_D2
     set  Data_D2             to  "k"
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "1"
     set  Write_enable_bar    to  "1"
end vector

vector   Data_written_D3
          drive  Data_D3
     set  Data_D3             to  "k"
     set  Address             to  "kkkkkkkkkkkk"
     set  Chip_enable_bar     to  "1"
     set  Write_enable_bar    to  "1"
end vector

vector   Data_In_D0_0
     initialize to Write_enabled
          drive  Data_D0
     set  Data_D0         to "0"
end vector

vector   Data_In_D0_1
     initialize to Write_enabled
          drive  Data_D0
     set  Data_D0         to "1"
end vector

vector   Data_In_D1_0
     initialize to Write_enabled
          drive  Data_D1
     set  Data_D1         to "0"
end vector

vector   Data_In_D1_1
     initialize to Write_enabled
          drive  Data_D1
     set  Data_D1         to "1"
end vector

vector   Data_In_D2_0
     initialize to Write_enabled
          drive  Data_D2
     set  Data_D2         to "0"
end vector

vector   Data_In_D2_1
     initialize to Write_enabled
          drive  Data_D2
     set  Data_D2         to "1"
end vector

vector   Data_In_D3_0
     initialize to Write_enabled
          drive  Data_D3
     set  Data_D3         to "0"
end vector

vector   Data_In_D3_1
     initialize to Write_enabled
          drive  Data_D3
     set  Data_D3         to "1"
end vector

vector   Read_Data_D0_0
     initialize to Output_valid
          receive  Data_D0
     set  Data_D0         to "0"
end vector

vector   Read_Data_D0_1
     initialize to Output_valid
          receive  Data_D0
     set  Data_D0         to "1"
end vector

vector   Read_Data_D1_0
     initialize to Output_valid
          receive  Data_D1
     set  Data_D1         to "0"
end vector

vector   Read_Data_D1_1
     initialize to Output_valid
          receive  Data_D1
     set  Data_D1         to "1"
end vector

vector   Read_Data_D2_0
     initialize to Output_valid
          receive  Data_D2
     set  Data_D2         to "0"
end vector

vector   Read_Data_D2_1
     initialize to Output_valid
          receive  Data_D2
     set  Data_D2         to "1"
end vector

vector   Read_Data_D3_0
     initialize to Output_valid
          receive  Data_D3
     set  Data_D3         to "0"
end vector

vector   Read_Data_D3_1
     initialize to Output_valid
          receive  Data_D3
     set  Data_D3         to "1"
end vector

!*****************************************************************************
!*****************************************************************************

sub  Write_Data (Address,Data)
      execute     Address
      execute     Chip_enabled
      execute     Data
      execute     Data_written
end sub

sub  Read_Data (Address,Data)
      execute     Address
      execute     Data
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_Data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_Data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_Data_Dx (Address, Data_Dx, Data_written_Dx)
      execute     Address
      execute     Chip_enabled
      execute     Data_Dx
      execute     Data_written_Dx
end sub

!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

     call Write_data_Dx (Address_000000000000, Data_In_D0_0, Data_written_D0)
     call Read_data (Address_000000000000, Read_data_D0_0)

     call Write_data_Dx (Address_000000000000, Data_In_D0_1, Data_written_D0)
     call Read_data (Address_000000000000, Read_data_D0_1)

end unit

unit   "awaretest D1 Test"

     call Write_data_Dx (Address_000000000000, Data_In_D1_0, Data_written_D1)
     call Read_data (Address_000000000000, Read_data_D1_0)

     call Write_data_Dx (Address_000000000000, Data_In_D1_1, Data_written_D1)
     call Read_data (Address_000000000000, Read_data_D1_1)

end unit

unit   "awaretest D2 Test"

     call Write_data_Dx (Address_000000000000, Data_In_D2_0, Data_written_D2)
     call Read_data (Address_000000000000, Read_data_D2_0)

     call Write_data_Dx (Address_000000000000, Data_In_D2_1, Data_written_D2)
     call Read_data (Address_000000000000, Read_data_D2_1)

end unit

unit   "awaretest D3 Test"

     call Write_data_Dx (Address_000000000000, Data_In_D3_0, Data_written_D3)
     call Read_data (Address_000000000000, Read_data_D3_0)

     call Write_data_Dx (Address_000000000000, Data_In_D3_1, Data_written_D3)
     call Read_data (Address_000000000000, Read_data_D3_1)

end unit


unit "RAM test"
     call Write_data (Address_000000000000, Data_In_0000)
     call Write_data (Address_000000000001, Data_In_0001)
     call Write_data (Address_000000000011, Data_In_0011)
     call Write_data (Address_000000000111, Data_In_0010)
     call Write_data (Address_000000001111, Data_In_0110)
     call Write_data (Address_000000011111, Data_In_0111)
     call Write_data (Address_000000111111, Data_In_0101)
     call Write_data (Address_000001111111, Data_In_0100)
     call Write_data (Address_000011111111, Data_In_1100)
     call Write_data (Address_000111111111, Data_In_1101)
     call Write_data (Address_001111111111, Data_In_1111)
     call Write_data (Address_011111111111, Data_In_1110)
     call Write_data (Address_111111111111, Data_In_1010)
     call Read_data (Address_000000000000, Read_data_0000)
     call Read_data (Address_000000000001, Read_data_0001)
     call Read_data (Address_000000000011, Read_data_0011)
     call Read_data (Address_000000000111, Read_data_0010)
     call Read_data (Address_000000001111, Read_data_0110)
     call Read_data (Address_000000011111, Read_data_0111)
     call Read_data (Address_000000111111, Read_data_0101)
     call Read_data (Address_000001111111, Read_data_0100)
     call Read_data (Address_000011111111, Read_data_1100)
     call Read_data (Address_000111111111, Read_data_1101)
     call Read_data (Address_001111111111, Read_data_1111)
     call Read_data (Address_011111111111, Read_data_1110)
     call Read_data (Address_111111111111, Read_data_1010)
end unit

unit "Chip_enable_false"
      call  Write_Data (Address_000000000000,Data_In_1111)
      execute  Address_000000000000
      execute  Chip_enable_false
      execute  Data_In_0000
      execute  Data_written
      call  Read_Data (Address_000000000000,Read_Data_1111)
end unit

!    End of test