!!!! 6 0 1 986588138 Vc3d8 ! Device : 6515h ! Function : Static RAM 1k x 8 ! revision : B.01.00 ! safeguard : med_out_mos ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." sequential warning "Pull-ups are required to test high-impedance outputs." assign VCC to pins 24 assign GND to pins 12 assign Address to pins 22,23,1,2,3,4,5,6,7,8 assign Chip_enable_bar to pins 18 assign Write_bar to pins 21 assign Output_enable_bar to pins 20 assign Data to pins 17,16,15,14,13,11,10,9 assign Data_D0 to pins 9 !AT Added for minimum pin test. assign Data_D1 to pins 10 !AT Added for minimum pin test. assign Data_D2 to pins 11 !AT Added for minimum pin test. assign Data_D3 to pins 13 !AT Added for minimum pin test. assign Data_D4 to pins 14 !AT Added for minimum pin test. assign Data_D5 to pins 15 !AT Added for minimum pin test. assign Data_D6 to pins 16 !AT Added for minimum pin test. assign Data_D7 to pins 17 !AT Added for minimum pin test. assign Y to pins 19 family TTL power VCC, GND inputs Address, Chip_enable_bar, Write_bar, Y, Output_enable_bar bidirectional Data bidirectional Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test. bidirectional Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test. when Chip_enable_bar is "1" inactive Data when Write_bar is "1" outputs Data when Write_bar is "0" inputs Data trace Data to Address, Chip_enable_bar, Write_bar, Y, Output_enable_bar disable Data with Chip_enable_bar to "1" set load on groups Data to pull up !***************************************************************************** !***************************************************************************** vector Address_0000000000 set Address to "0000000000" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0000000001 set Address to "0000000001" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0000000011 set Address to "0000000011" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0000000111 set Address to "0000000111" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0000001111 set Address to "0000001111" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0000011111 set Address to "0000011111" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0000111111 set Address to "0000111111" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0001111111 set Address to "0001111111" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0011111111 set Address to "0011111111" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_0111111111 set Address to "0111111111" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Address_1111111111 set Address to "1111111111" set Chip_enable_bar to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector vector Data_read_00000000 receive Data set Chip_enable_bar to "0" set Data to "00000000" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_00000001 receive Data set Chip_enable_bar to "0" set Data to "00000001" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_00000011 receive Data set Chip_enable_bar to "0" set Data to "00000011" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_00000111 receive Data set Chip_enable_bar to "0" set Data to "00000111" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_00001111 receive Data set Chip_enable_bar to "0" set Data to "00001111" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_00011111 receive Data set Chip_enable_bar to "0" set Data to "00011111" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_00111111 receive Data set Chip_enable_bar to "0" set Data to "00111111" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_01111111 receive Data set Chip_enable_bar to "0" set Data to "01111111" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_11111111 receive Data set Chip_enable_bar to "0" set Data to "11111111" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_11111110 receive Data set Chip_enable_bar to "0" set Data to "11111110" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_11111100 receive Data set Chip_enable_bar to "0" set Data to "11111100" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_write_00000000 drive Data set Chip_enable_bar to "0" set Data to "00000000" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_00000001 drive Data set Chip_enable_bar to "0" set Data to "00000001" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_00000011 drive Data set Chip_enable_bar to "0" set Data to "00000011" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_00000111 drive Data set Chip_enable_bar to "0" set Data to "00000111" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_00001111 drive Data set Chip_enable_bar to "0" set Data to "00001111" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_00011111 drive Data set Chip_enable_bar to "0" set Data to "00011111" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_00111111 drive Data set Chip_enable_bar to "0" set Data to "00111111" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_01111111 drive Data set Chip_enable_bar to "0" set Data to "01111111" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_11111111 drive Data set Chip_enable_bar to "0" set Data to "11111111" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_11111110 drive Data set Chip_enable_bar to "0" set Data to "11111110" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_11111100 drive Data set Chip_enable_bar to "0" set Data to "11111100" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector End_cycle set Chip_enable_bar to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "1" end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector Data_read_D0_0 receive Data_D0 set Chip_enable_bar to "0" set Data_D0 to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D0_1 receive Data_D0 set Chip_enable_bar to "0" set Data_D0 to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D1_0 receive Data_D1 set Chip_enable_bar to "0" set Data_D1 to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D1_1 receive Data_D1 set Chip_enable_bar to "0" set Data_D1 to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D2_0 receive Data_D2 set Chip_enable_bar to "0" set Data_D2 to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D2_1 receive Data_D2 set Chip_enable_bar to "0" set Data_D2 to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D3_0 receive Data_D3 set Chip_enable_bar to "0" set Data_D3 to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D3_1 receive Data_D3 set Chip_enable_bar to "0" set Data_D3 to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D4_0 receive Data_D4 set Chip_enable_bar to "0" set Data_D4 to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D4_1 receive Data_D4 set Chip_enable_bar to "0" set Data_D4 to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D5_0 receive Data_D5 set Chip_enable_bar to "0" set Data_D5 to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D5_1 receive Data_D5 set Chip_enable_bar to "0" set Data_D5 to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D6_0 receive Data_D6 set Chip_enable_bar to "0" set Data_D6 to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D6_1 receive Data_D6 set Chip_enable_bar to "0" set Data_D6 to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D7_0 receive Data_D7 set Chip_enable_bar to "0" set Data_D7 to "0" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_read_D7_1 receive Data_D7 set Chip_enable_bar to "0" set Data_D7 to "1" set Write_bar to "1" set Y to "1" set Output_enable_bar to "0" end vector vector Data_write_D0_0 drive Data_D0 set Chip_enable_bar to "0" set Data_D0 to "0" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D0_1 drive Data_D0 set Chip_enable_bar to "0" set Data_D0 to "1" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D1_0 drive Data_D1 set Chip_enable_bar to "0" set Data_D1 to "0" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D1_1 drive Data_D1 set Chip_enable_bar to "0" set Data_D1 to "1" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D2_0 drive Data_D2 set Chip_enable_bar to "0" set Data_D2 to "0" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D2_1 drive Data_D2 set Chip_enable_bar to "0" set Data_D2 to "1" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D3_0 drive Data_D3 set Chip_enable_bar to "0" set Data_D3 to "0" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D3_1 drive Data_D3 set Chip_enable_bar to "0" set Data_D3 to "1" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D4_0 drive Data_D4 set Chip_enable_bar to "0" set Data_D4 to "0" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D4_1 drive Data_D4 set Chip_enable_bar to "0" set Data_D4 to "1" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D5_0 drive Data_D5 set Chip_enable_bar to "0" set Data_D5 to "0" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D5_1 drive Data_D5 set Chip_enable_bar to "0" set Data_D5 to "1" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D6_0 drive Data_D6 set Chip_enable_bar to "0" set Data_D6 to "0" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D6_1 drive Data_D6 set Chip_enable_bar to "0" set Data_D6 to "1" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D7_0 drive Data_D7 set Chip_enable_bar to "0" set Data_D7 to "0" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector vector Data_write_D7_1 drive Data_D7 set Chip_enable_bar to "0" set Data_D7 to "1" set Write_bar to "0" set Y to "1" set Output_enable_bar to "1" end vector !***************************************************************************** !***************************************************************************** sub R_W_data (Address,Data) execute Address execute Data execute End_cycle end sub !***************************************************************************** !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with D0. unit "awaretest D0 Test" call R_W_data (Address_0000000000,Data_write_D0_0) call R_W_data (Address_0000000000,Data_read_D0_0) call R_W_data (Address_0000000000,Data_write_D0_1) call R_W_data (Address_0000000000,Data_read_D0_1) end unit unit "awaretest D1 Test" call R_W_data (Address_0000000000,Data_write_D1_0) call R_W_data (Address_0000000000,Data_read_D1_0) call R_W_data (Address_0000000000,Data_write_D1_1) call R_W_data (Address_0000000000,Data_read_D1_1) end unit unit "awaretest D2 Test" call R_W_data (Address_0000000000,Data_write_D2_0) call R_W_data (Address_0000000000,Data_read_D2_0) call R_W_data (Address_0000000000,Data_write_D2_1) call R_W_data (Address_0000000000,Data_read_D2_1) end unit unit "awaretest D3 Test" call R_W_data (Address_0000000000,Data_write_D3_0) call R_W_data (Address_0000000000,Data_read_D3_0) call R_W_data (Address_0000000000,Data_write_D3_1) call R_W_data (Address_0000000000,Data_read_D3_1) end unit unit "awaretest D4 Test" call R_W_data (Address_0000000000,Data_write_D4_0) call R_W_data (Address_0000000000,Data_read_D4_0) call R_W_data (Address_0000000000,Data_write_D4_1) call R_W_data (Address_0000000000,Data_read_D4_1) end unit unit "awaretest D5 Test" call R_W_data (Address_0000000000,Data_write_D5_0) call R_W_data (Address_0000000000,Data_read_D5_0) call R_W_data (Address_0000000000,Data_write_D5_1) call R_W_data (Address_0000000000,Data_read_D5_1) end unit unit "awaretest D6 Test" call R_W_data (Address_0000000000,Data_write_D6_0) call R_W_data (Address_0000000000,Data_read_D6_0) call R_W_data (Address_0000000000,Data_write_D6_1) call R_W_data (Address_0000000000,Data_read_D6_1) end unit unit "awaretest D7 Test" call R_W_data (Address_0000000000,Data_write_D7_0) call R_W_data (Address_0000000000,Data_read_D7_0) call R_W_data (Address_0000000000,Data_write_D7_1) call R_W_data (Address_0000000000,Data_read_D7_1) end unit unit "Ram Test" ! initialize ram call R_W_data (Address_0000000000,Data_write_00000000) call R_W_data (Address_0000000001,Data_write_00000001) call R_W_data (Address_0000000011,Data_write_00000011) call R_W_data (Address_0000000111,Data_write_00000111) call R_W_data (Address_0000001111,Data_write_00001111) call R_W_data (Address_0000011111,Data_write_00011111) call R_W_data (Address_0000111111,Data_write_00111111) call R_W_data (Address_0001111111,Data_write_01111111) call R_W_data (Address_0011111111,Data_write_11111111) call R_W_data (Address_0111111111,Data_write_11111110) call R_W_data (Address_1111111111,Data_write_11111100) ! test ram cells call R_W_data (Address_0000000000,Data_write_00000000) call R_W_data (Address_0000000001,Data_write_00000001) call R_W_data (Address_0000000011,Data_write_00000011) call R_W_data (Address_0000000111,Data_write_00000111) call R_W_data (Address_0000001111,Data_write_00001111) call R_W_data (Address_0000011111,Data_write_00011111) call R_W_data (Address_0000111111,Data_write_00111111) call R_W_data (Address_0001111111,Data_write_01111111) call R_W_data (Address_0011111111,Data_write_11111111) call R_W_data (Address_0111111111,Data_write_11111110) call R_W_data (Address_1111111111,Data_write_11111100) call R_W_data (Address_0000000000,Data_read_00000000) call R_W_data (Address_0000000001,Data_read_00000001) call R_W_data (Address_0000000011,Data_read_00000011) call R_W_data (Address_0000000111,Data_read_00000111) call R_W_data (Address_0000001111,Data_read_00001111) call R_W_data (Address_0000011111,Data_read_00011111) call R_W_data (Address_0000111111,Data_read_00111111) call R_W_data (Address_0001111111,Data_read_01111111) call R_W_data (Address_0011111111,Data_read_11111111) call R_W_data (Address_0111111111,Data_read_11111110) call R_W_data (Address_1111111111,Data_read_11111100) end unit ! End of test