At this seminar, Keysight’s technical experts and application engineers will demonstrate the most advanced design and test solutions for PCIe Gen 5, 400G/800G PAM4, Terabit Coherent Optical (*DDR5/LPDDR5), and signal integrity measurement. Our broad expertise is built on continuing involvement with industry experts, and our high-speed digital test solutions span across all stages of the design cycle: design and simulation, analysis, debug, and compliance testing.

Learn the latest techniques to help uncover problems, optimize performance, and deliver your design on time and within budget. Register today for a High-Speed Digital Seminar near you.


8:30 a.m.

9:00 a.m. – 3:45 p.m.


Dates and Locations


8:30 am / Registrations

9:00 am / TDECQ for PAM4 Optical Transmitters: Does it Really Work?

The use of PAM4 and forward error correction led to dramatic changes in the test methods used to characterize optical transmitters used in digital communications systems. TDECQ (transmitter dispersion and eye closure quaternary) is the primary example of this change. Does the measurement really provide the results it was intended to yield, specifically the power penalty metric needed to predict how well a transmitter will operate in a real system? This paper will try to document when it does and when it does not.

9:45 am / 400G: Looking Forward to 800G

Most of the work on the '400G Class' Standards is complete, and new projects are starting to define the electrical links that will enable the next '800G Class' of optical and electrical standards. The low margins we see today will be even smaller or non-existent in the next generation. Verifying compliance for 400G requires careful attention to test setup and execution and will likely require even more discipline moving forward. This session will cover practical techniques to minimize some of the problem areas users are experiencing today in validating compliance in 400G links, and what challenges we may see as the '800G Class' Standards begins to take shape.

10:45 am / Break

11:15 am / PCI Express 5.0: Full Speed Ahead! Phy Layer Testing Challenges at 32GT/s

Only two years in the making, PCI Express 5.0 is quickly following on the heels of the PCIe 4.0 specification and is expected to be finalized in H1 2019. At speeds of 32GT/s, and across channels that conspire to attenuate the 32GT/s signal by up to -38dB of loss at 16Ghz, PCIe 5.0 portends to become the most challenging edition of the PCI Express standard to date. In this session, you will learn about some of the key differences between PCI Express 5.0 and PCIe 4.0 including changes to the Gen5 receiver equalization requirements along with new options for link equalization. Especially challenging for Gen5 is the need to be able to tolerate an eye height of just over 10mV which is expected to push receiver technology to the brink. In this session, you'll learn not only what's new with the PCIe 5.0 standard but also what to look for as you evaluate tools to help you validate your transmitter and receiver circuits.

12:30 pm / Lunch

1:30 pm / A Practical Guide to Signal Integrity: From Simulation to Measurement

Hyperscale data centers are a critical component of today's internet infrastructure. This architecture requires extreme bandwidth over everything copper and demands next level design techniques and analysis tools in the signal integrity lab. This presentation will clarify how to achieve the highest practical Signal Integrity (SI) of the physical layer by analyzing an example channel with mixed-mode S-parameters, eye diagram, time domain reflectometry (TDR), and single pulse response in both simulation and measurement. In addition, a case study for PCI express will demonstrate the usage of IBIS-AMI models with equalization on both transmitter and receiver. After fabricating and measuring the example channel, SI analyses will be shown to demonstrate the importance of a robust SI measurement and simulation workflow.

If you are new to signal integrity, this session will give you a head start on your journey, including complimentary example files for continuing your learning. For experienced SI engineers, this presentation is an excellent refresher on the fundamental SI analyses and concepts in both simulation and measurement.

2:30 pm / Break

2:45 pm / Terabit Communication Research with Coherent Optical Modulation Tools

The ever-growing demand for higher transmission capability will soon drive coherent modulation symbol rates to 64 GBaud and to the 100 GBaud range in the long term. To keep up with this symbol rate increase, test instruments that can handle the symbol rate classes of transceivers for 600 Gb/s, 1.2 Tb/s and beyond are required. Modulation formats are also getting more demanding due to the higher-order quadrature amplitude modulation which requires a step forward in noise performance.

If you plan to use coherent modulation for higher bit rates, this session introduces you to the basic concepts of coherent signal measurements, new advanced tools, and provides examples of measurements.

2:45 pm / Get Your Game On for Next Generation DRAM: DDR5 and LPDDR5 (*Vancouver ONLY)

Right on the heels of DDR4, the industry's next generation of system and mobile memories will drive another paradigm shift for Silicon and system developers. DDR4 required thinking to move beyond the certainty promised by setup and hold timings and voltage margins into the new terrain of random and deterministic jitter and noise as well as bit error rates (BER) that could never be guaranteed to be zero no matter how much margin you had. This is the world of data eyes and statistics. Before DDR4 speeds can be doubled, the statistical eye that people were just getting their minds wrapped around will collapse. Opening it back up requires applying concepts first developed for high-speed serial buses like PCI Express to DDR. Memory's wide, single ended, bidirectional and bursty bus stretches these concepts to their limits and beyond, requiring everyone to up their game. This session will show you how to get your game on so you can master a whole new generation of DRAM.

3:45 pm / End of event

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