Three Secrets to Success for DDR5 Memory Designs
Double data rate (DDR) memory has been around since the 1990s. Engineers who have worked on DDR since the beginning have developed and perfected their ideal memory design workflow. Since its development, DDR memory technology has advanced considerably.
With transfer rates up to 6.4 Gbps, the latest standard for DDR meets the insatiable “need for speed” of today’s electronics. But like any new standard, DDR5 also comes with its design challenges.
The new memory standards challenge the preceding methods of memory design. With equalization and eye measurements required in the new standard, the traditional SPICE simulation methods don’t hold up in today’s design world.
Hardware engineers need to minimize the risk of signal integrity issues in memory bus designs, which requires the ability to predict the signal quality after equalization, prototype the design and test for performance.
A robust design to test memory workflow is the key to success. Here are three ways to create a robust design to test memory workflow and achieve success at DDR5 speeds.
1. Use accurate IBIS-AMI models for advanced analysis
When using algorithmic modeling interface (AMI) device modeling, the GetWave function only has a data signal as an input. This function cannot model the physical clocking behavior.
The new getWave2, implemented in PathWave Memory Designer, captures the clock signal. With additional timing information, simulation can better model device operation.
Figure 1. IBIS AMI models enable advanced analysis including DSP and equalization.
For example, jitter tracking shows the modeling of the physical receiver clocking behavior. Memory Designer takes in the IBIS model, the analog behavior, with the AMI portion of the digital signal processing (DSP), including equalization. This makes it easy to validate system performance.
By using accurate IBIS-AMI models that enable advanced analyses, you can easily identify DFE equalization settings, predict measurement with simulation, and extend the usage of your current design.
2. Adopt a “smart” design process
An AMI model specifies different device parameters to represent the physical behavior. PathWave Memory Designer has a built-in AMI model builder so you can easily generate industry-standard models. The models can easily be used in a simulation as the controller, or the memory.
The Smart Bus Wire connecting the components (Figure 2) makes all the interconnections with only one click. The Smart Components can handle circuit cells, netlists, or electromagnetic (EM) analysis data.
Figure 2. The smart bus wire in Memory Designer connects the design components in a single click.
The memory probe also offers design exploration that helps you check the pass/fail status of different customized testing conditions (Figure 3). By integrating the smart, productive, and streamlined memory design process, you can explore the complexities of your design space, predict eye-opening with confidence, and increase memory design productivity.
Figure 3. The memory probe performs in-depth design exploration that provides the pass/fail status of different testing conditions.
3. Stay in a Cohesive Software Environment
Between design and test, there is a lot of chance for risk. If there are too many steps involved in completing a task, one small mistake can ruin the entire process. A cohesive design to test environment can minimize the risk. PathWave Memory Designer easily connects to Infiniium scope software and offers industry-accepted compliance test apps and reports.
Figure 4. Memory Design connects PathWave ADS software to Infiniium compliance test apps for a complete design to test workflow.
With Memory Designer, you can unify your design to test software, test with industry-accepted apps, and get the detailed compliance reports that you want.
To learn more about how Memory Designer streamlines the DDR5 memory design workflow, watch this video: 3 Ways to Avoid Failing at DDR5 Speeds
Request a 30-day trial of Memory Designer today: http://www.keysight.com/find/mytrial.si.vi