What Is Register-Transfer-Level (RTL) Design?
Register-transfer-level (RTL) design is an essential step in the digital circuit design process. It defines and optimizes the logical functionality of a digital design at an abstract level before specifying the circuit’s physical layout. Engineers convert the high-level desired behavior of their design to software code using a hardware description language (HDL) like very high-speed integrated circuit hardware description language (VHDL) or Verilog.
The first HDLs capable of modeling at the RTL level were developed in the 1980s and evolved into full design systems that enable engineers to model the data flow in electronic circuits.
As designs became larger and more complex and manufacturing technology enabled new ways of carrying out logical and mathematical operations, RTL design methods kept pace. Over time RTL design became a required step in the digital design process that bridges the system specification and the circuit design steps.
The abstract nature of the RTL description allows for quick studies and fast design iterations to obtain an acceptable and optimized design before delving into the more complex and time-consuming phases of the design process. Engineers can optimize their designs at the register, operator, and data flow stages before they need to start worrying about the physical components and how they’re connected.
In this article, we’ll cover some fundamentals, describe where RTL design fits into digital circuit design, and explain the RTL design flow. We’ll then show how RTL design fits into field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) chip design and reveal what the future of RTL design looks like.
The fundamentals of RTL design
The phrase “register-transfer” refers to the data flow between registers and how to apply logical operations and mathematical operations to the data. Engineers use RTL design to describe functional blocks, so as to define the behavior of a discrete component used to execute a specific function. Each functional block has a description of the registers in the block, referred to as the sequential circuit, and a combinational circuit that contains the logical operation for the functional block. They also use the HDL to describe how functional blocks are connected to define data flow through the circuit.
RTL design lets engineers take a complex system and break it up into relatively simple blocks represented by HDL code. Here are a few key fundamentals of RTL design.
Registers
In RTL design, a hardware element that can store a set amount of data is called a register and is usually implemented as D flip-flops. You can read a register’s value as input to a logical operation, or set it as the output of an operation. Characterizing how data flows between registers and how an operation changes the data is RTL design’s fundamental purpose.
Hardware description language (HDL)
The most important part of RTL design is the code that describes a circuit’s behavior. An HDL is a specification language that looks a lot like a programming language, with variables, function calls, logical if-then-else or case statements, Boolean statements, and math.
However, HDLs are specifically designed to describe the behavior and structure of electronic circuits, usually integrated circuits (ICs). One thing that sets HDLs apart from programming languages is that the concept of time is included within HDLs so that a circuit’s clocks can trigger operations.
This is accomplished by using a variable that defines a digital clock’s value in the circuit, as in this VHDL simple example of an inverter where the output (Q) is set to the input value (D) when the clock value (clk) goes from a low to a high state (rising edge):
D <= not Q;
process(clk)
begin
if rising_edge(clk) then
Q <= D;
end if;
end process;
Figure 1. HDLs example
VHDL, the most commonly used HDL, is a verbose, strongly typed language with a syntax that doesn’t look like the C language. It’s the preferred HDL for describing more complex system designs.
Another common HDL, Verilog or its superset SystemVerilog, is more concise, weakly typed, and flexible, and its syntax looks like C code. Because it’s easy to learn and use to create descriptions, engineers prefer it when starting out or when their circuits are not as complicated. The Institute of Electrical and Electronics Engineers (IEEE) defines both Verilog and VHDL as industry standards.
Here’s a simple example of an AND gate in both languages. An AND gate has two inputs and one output. If the inputs are both equal to 1, the output is 1. If they are not equal or if both are set to 0, the output is 0.
VHDL describes an AND gate as:
entity my_and is -- First, you define the entity
port (
inp1: in std_logic; -- The first port
inp2: in std_logic; -- The second port
rst: out std_logic -- The output port
);
end my_and;
architecture blk of my_and is -- Next, define the architecture
begin
process(inp1, inp2) -- With the inputs, do the following
Begin
-- Use a simple if-then-else statement
if((inp1=’1’) and inp1=’1’))then
rst <= ’1’;
else
rst <= ’0’;
End if;
end process
end blk;
Figure 2. AND gate example
The Verilog for the AND gate looks like this:
module my_and(inp1,inp2,rst); // define the module call
input inp1, inp2; // define inputs and output
output rst;
assign rst = inp1 & inp2; // use the & (and) operator
Endmodule
Figure 3. Verilog for the AND gate example
The logic takes the value at the two input ports and sets the output to 1 if both ports are 1. This is a simple example, but this type of code can represent every entity in the system and can then be combined to define an entire digital circuit. Typical basic building blocks include adders, multipliers, counters, memory, and state machines. Once a design engineer defines the system, the code is sent to a compiler. If it compiles with no errors, the engineer can use the result to test their system.
Logical operations
There are two types of operations in RTL design. The first is logical operations, which perform bitwise evaluation and modification of the data stored in registers. Engineers can define the logical behavior in the HDL to create logical operations like AND, OR, NOT, XOR, and shift. The example above shows how an AND can be represented in VHDL and Verilog. Logical operations represent logic gates in the hardware.
Arithmetic operations
The second type of operations in RTL design are arithmetic operations. They take the data in registers and add, subtract, multiply, and divide. They are represented in the HDL with standard mathematical operators. As an example, adding two numbers in VHDL would use the line:
Figure 4. Adding two numbers in VHDL
This is where inp1 and inp2 are two input registers, and rst is assigned to the output register. Arithmetic operations in RTL represent dedicated physical elements such as adders, subtractors, multipliers, and dividers.
Synchronous and asynchronous actions
The RTL design can represent data flow in either a synchronous or an asynchronous manner. For synchronous, a routine is executed, or triggered, by the system clock input to the function. For asynchronous, the routine is executed when a value of one or more input ports changes in a specific way. This is implemented by checking the values of the clock input or the non-clock inputs to see if they have changed with an if-statement.
RTL’s role in integrated circuit design
Modern IC design flow involves taking a specification for what the device needs to do and turning it into a packaged semiconductor chip. RTL design delivers a level of abstraction that enables engineers to concentrate on the system’s higher-level functions without the need to consider the particulars of how to physically implement the design.
Figure 5. The IC design process. RTL design bridges the system specification and the circuit design step.
The first step in an IC design flow is to define the system specifications and the architectural design. This information gets converted into HDL code. Engineers then use that code to define the functional and logical design. Once that is completed, the design gets converted into a netlist, which is then used to create the circuit design, followed by the rest of the design process.
The abstract representation using RTL design is done as early in the design process as possible — before time and money are spent on the physical design, verification of the physical design, or actual hardware fabrication. Fitting the RTL design step into the process requires good integration at the start between system specification and strong tools that convert the registers, operations, and data flow into an actual circuit when the RTL design is done.
The RTL design flow
The goal of the RTL design flow is to define and optimize the functionality of an integrated circuit, usually an FPGA or ASIC device. Design engineers use the RTL design flow to first define a device’s logic and flow to test and optimize the system, then convert the RTL definition to a netlist. The following five steps define typical RTL design methodology.
1. High-level synthesis
The first task in the flow is to convert a device’s specifications into HDL code with as few edits as possible. In most cases, engineers represent the desired behavior of the device in a standard programming language like C or C++. A software tool then breaks down the algorithms in the software model into the chosen specification language. Engineers can skip this step for simpler designs, but can save a considerable amount of effort by employing this step for more complex designs.
2. RTL coding
Engineers then create or refine the code, getting into the details of specific registers, the operations they need, and how the data flows. One important part of this step is the use of modules to describe common operations and specific parts of the system. Engineers can reuse modules where applicable, greatly simplifying overall design complexity.
3. Optimization of performance, power, and area (PPA)
Once coding is complete, the optimization process begins. The goal is to improve performance, minimize power usage, and reduce the design’s physical size.
Timing and logic simulation: Design engineers use simulation tools to conduct timing analysis and track register values throughout the system. They check the design at the register-transfer level to ensure there are no timing issues across the circuit and that the operations produce the expected outputs. And they work to debug any system-related issues, including power glitches, as early as possible in the design process.
Power estimation: Each device in the system consumes some amount of power, and design engineers need to know how much power is being consumed and iterate on their design to manage power distribution and minimize power consumption. Many leading semiconductor design companies use Keysight PowerArtist software to analyze, profile, and reduce power at the register-transfer level. PowerArtist enables a fast turnaround that allows design teams to slice and dice power, identify power-inefficient RTL code, and tag every wasted toggle in the design.
Area minimization: Every IC component takes up physical space, as does the routing between those components. Although the RTL design process doesn’t look at components’ physical size, it does capture how many components there are and the complex connections between them.
4. Verification
Once they’ve optimized the design, engineers must verify it with RTL simulation or formal verification. It’s critical that the design achieves all requirements before it can move forward.
RTL simulation: Engineers employ various software tools to dynamically verify the design. Input vectors are applied, and the resulting output vectors are compared to the expected results. The inputs and outputs are usually represented as waveforms so that the design engineer can visually inspect the system’s behavior.
Formal verification: This static verification process uses automation to convert a set of behavior expectations into mathematical algorithms that explore a system’s entire operating space. The results are then mathematically evaluated to verify correctness.
5. RTL synthesis
Following verification, engineers use RTL synthesis to convert the HDL code representation of RTL design into a gate-level netlist. This is the front end for tools that convert the resulting schematic into a physical layout in an electronic design automation (EDA) tool.
Using RTL design in FPGA and ASIC design flows
Integrated circuits comprise two classes: ASICs or FPGAs. ASICs are custom designed for specific applications or tasks. Once built, a chip’s logic cannot be changed. Examples of ASIC chips are memory modules, digital voice recorders, optimized signal processors, microprocessors, central processing units (CPUs), or even something as complex as a system on a chip that includes I/O, CPU, memory, and more.
FPGA chips are semiconductor chips that engineers can reprogram after they’re manufactured. Instead of having logic built into a chip’s geometry, FPGAs have arrays of logical blocks connected by a connection grid that engineers can program.
RTL design plays the same role in the first part of both design flows. Once RTL synthesis is complete, the ASIC design flow requires engineers to plan and lay out the physical circuits, called floorplanning. In an FPGA design, RTL code is converted directly into a netlist that knows what logical blocks are available and configures those blocks in the place and route step.
The future of RTL design
The use of hardware description languages to represent the desired behavior of digital systems started in the 1970s and 1980s. It found significant favor as very large-scale integration (VLSI) grew in popularity and has kept pace with further developments in IC design. As IC feature size continues to shrink, clock speeds continue to increase, and more functionality is packed into one chip, design engineers face increasing challenges.
Design complexity has not slowed down, and RTL tools continue to rise to these challenges. The companies developing the tool suites that designers will use to define next-generation ICs will focus on a few key areas to improve ease of use, capability, and functionality of the RTL design flow, including:
- Power reduction
One of the biggest challenges across the entire IC design process is power management. RTL optimization continues to effectively aid design teams in understanding and managing the voltage drops that consume power in a system. Enhancements to tools, such as PowerArtist software, that bring more options, greater visibility, and increased speed will help teams meet this challenge.
- Seamless integration between tools
As the number of tools available for design, simulation, verification, and signoff increases, the capabilities of existing tools will also increase. Companies producing these tools and industry organizations like IEEE will need to keep pace by updating and improving standards and providing tools that can support a seamless flow between applications.
- Inclusion of artificial intelligence (AI) in the design flow
Many tools used in the IC design process have used forms of machine learning (ML) and expert systems to speed process steps, especially in the layout of physical circuits. This will only continue with improved ML algorithms and the use of generative AI tools to suggest the most probable next steps or solutions.
- Improvements to high-level synthesis
RTL vendors are working hard to improve engineers’ ability to convert their high-level system specification to high-level hardware languages with greater speed, and with designs that come closer to the optimal configuration.
- Smarter RTL synthesis
There’s room for significant gains in productivity and optimization when the gates in an RTL description are converted into actual transistors in the RTL synthesis step. As physical geometry enters the design, engineers can make informed decisions that will simplify the downstream processes of laying out the circuit.