With PCIe® 6.0 You Have to Move from NRZ to PAM4... But What is PAM4 signaling?
4-level pulse amplitude modulation (PAM4) is an evolution from the two state non-return-to-zero (NRZ) modulation that has been used throughout the PCIe ® v1.0 to the PCIe v5.0 revisions of the PCIe standard. In NRZ one bit is transmitted per symbol (or unit interval UI) versus two per UI (or symbol) in PAM4. This means the data rate is doubled while the channel bandwidth is kept constant. This is possible by using 4 amplitude levels instead of 2 (see figure 1). The absolute amplitude between lowest and top level stays the same though introducing new signal integrity issues as we will see.
Figure 1 Principle of NRZ versus PAM4 signaling
PCIe 6.0 technology will double the maximum bandwidth of the PCIe v5.0 standard to 256 GT/s assuming the same maximum number of lanes, 16. The data transfer rate will hit 64 GT/s per lane, up from PCIe 5.0's maximum data rate of 32 GT/s. A move from NRZ to PAM4 with PCIe 6.0 was inevitable.
PAM4 effectively doubles the data rate without demanding extra link bandwidth at the expense of reduced signal to noise ratio (SNR). You require new measurements to characterize impairments that were not an issue in previous NRZ designs. We can help you ensure accurate and repeatable results to accelerate the development of your PAM4 interface components and systems.
Learn about the design and test challenges of migrating from NRZ to PAM4
As the data rate increases using PAM4 multi-level signaling in serial interconnects, the rise time of the data transition from level zero to level three becomes faster. This faster rise time creates larger reflections at impedance discontinuities and degrades the signal quality at the end of the channel. As a result, you need to account for signal degradation due to physical layer components such as printed circuit board traces, connectors, cables, and integrated circuit (IC) packages when testing the performance of your PAM4 devices.
Figure 2 Eye diagram of an NRZ and a PAM4 signal
With PAM4, the signal to noise ratio gets lowered by 33% (9.5 dB) which exacerbates the signal degrading effects described above. To account for the higher noise sensitivity, starting with PCIe Version 6.0, forward-error-correction (FEC) becomes mandatory.
Learn how to analyze PAM4 receiver signals
In our next PCIe blog, we’ll introduce you to the PCIe v6.0 TX measurement requirements such as SNDR (signal-to-noise and distortion ratio), RLM (ratio of level mismatch) and multi-edge jitter standard.