I need to measure a load accurately for a one port measurement. The problem is there are other devices interposed between my load and port 1 of my VNA such as adapters, fixturing connectors, etc.. I would like to use the NA's TDR function as a means to set gate start and stop times so that I may measure only my load in isolation.
Generally, the method to make this type is measurement is to set the gate start and stop times and then disable the transform function (although gating is enabled) and then view the load on a Smith Chart.
My question is this, in order to mark the best start and stop times using the gating function, what TDR function is best to use to "mark" the gate start and stop time.
I like to use the the impulse response function to mark the start gate time. I generally set the start time at the peak of the impulse response when I am certain I have detected the physical position of the load. Can you tell me, for the most accurate measurement measurement of my load should I set the start time at the base of the impulse response at the load point (the base point I am referring to marks the beginning of the upward slope of the impulse signal) or at the peak of the impulse response? Keep in mind the measurement I am making does not use the impulse response to make the measurement of the load itself, the impulse response is only used to mark the start gate time before I disable the TDR option (but gating is enabled).
To determine the optimum stop gate time to capture data referenced to only the load is the primary reason why I have written this post, can you tell me how I should go about determining the best gate stop time to make the most accurate measurement of my load?
It's quite complicated to understand the proper gating effects for gating out a load. I explain much of this in Chapter 4 or my new book (it takes about 20 pages to fully explain gating and gating compensation).
The effects that must be included are:
Compensating for lost energy to to gating out connectors preceeding the DUT
Compensating for gate re-normalization due to non-symmetric gate responses
Compensating for gate shape effects
In practice, the last two effects occur only in the last 10% of the frequency response, if low-pass mode is used.
The gate start should be set at least one gate width before the onset of the DUT time-domain response. The gate stop should be set to center the DUT response in the gate. Wider gate widths generate smaller edge effects so make the gate as wide as practial while keeping the response centered on the DUT.
I forget the exact wording, but it is something like gate rise time. The gate has a rise time and 2x is the gate width, so you should be sure the gate start is before the DUT response by at least one rise time or probably at least 2 to ensure no effect from gate rise effects.
Can you tell me if gate rise time is specified in the NA manual?
If "gate rise time" is not specificed can you please provide me with an equation, observed gate rise time by inspection, or an experimental set up to determine gate rise time?
Also, with regard to "stop time," for a one port measurement, where the load is the last element in the circuit, should I position the stop time at a time before the point in time when the second impulse signal arises (the second impulse signal is an undesired signal)?