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Designing Scalable 10G Backplane Interconnect Systems

Technical Overviews

Introduction

The design and implementation of high-speed backplanes requires substantial effort both in pre-pro­totype modeling and post-prototype testing and measuring. Extant methods for modeling backplane signal paths have become very sophisticated and time consuming. Correspondingly, current test methods for verification of design have relied on direct measurement techniques which are often useful for only a single test condition requiring multiple test runs. This paper presents techniques for design which significantly reduce modeling requirements for the design of high-speed backplanes in conjunction with advanced testing techniques which provide maximum channel characterization with the minimum amount of time.

Companies requiring 10 Gb/s (and higher rates) backplane solutions all face the same challenges of cost, power, scalability and integration. The current standard design approach of embedding back­plane SERDES I/O within ASICs, to save cost and extend performance, has been effective for 3G and for some 6G backplanes. At 10G, issues of signal loss due to material, cross-talk and power consump­tion make it, at best, risky and more costly to pursue the same design and testing approaches as previous generations.

Instead of relying entirely upon electronic enhancements based on SERDES technology, an improve­ment of channel capability is proposed for the high-speed signals. Multiple benefits are created by improving the channel for high-speed signals. First, materials can be selected which reduce the inser­tion loss and consequently reduce I/O power requirements. Signal path structures can be optimized to minimize signal distortion thereby further reducing I/O power consumption due to relaxed signal recovery timing requirements. Cross-talk, a major component of signal integrity, can also be signifi­cantly minimized contributing to a lowering of overall signal-to-noise considerations in the signal receiver. Improved channel construction holds the promise of much higher bit rates than a particular design point. For example, a channel which has been improved for use at 10 Gb/s could easily be considered for use at 12, 15 or even 20 Gb/s given the proper I/O electronics. The current methodolo­gy for analyzing a channel and its performance is a resource intensive activity given the cost and time associated with test setup and analysis. Projecting the performance of a channel at multiple bit rates is time consuming and arduous when one considers the non-linearities associated with traditional channel construction operating at different frequencies. The idea of a singular design point has also permeated the back end of product design wherein testing and verification has been limited to the intended operating point (e.g. 10 Gb/s).

Given the challenges of 10G design and development, it is clear that an updated test and measuring methodology is needed to take advantage of improved signal channel capability. Performance data collected at a single operating point, while useful, is certainly not efficient when there is need to extrapolate product performance into the future. Thus the approach taken for this project is to expand the test and measurement of the signal channel to include a full characterization of its properties over a 10x range of operating frequencies. The resulting performance data, in the form of S-parameters, is then used to construct performance characteristics from different operating points through the use of accurate modeling transformations. Significant savings in testing are gained since accurate test results (TDR plots and eye-patterns) from different operating points are synthesized conveniently without having to continuously return to a test lab.

Current Design Approaches and Impediments

Powerful evolutionary forces in product design conspire to keep incremental improvement approaches in play for as long as possi­ble to forestall the expense of new technology adoption. Back­plane and chassis construction certainly adhere to these condi­tions and no doubt will continue on into the foreseeable future.

For many backplane generations, the issues of impedance, loss, signal stubs, lumped parasitic and cost have been in the forefront of design considerations. As bit rates have risen over time, the deleterious effects of the aforementioned elements on the signal quality have increased significantly and so also has I/O circuit design complexity. To combat the increase in signal degradation issues, electrical engineers, along with electro-me­chanical engineers have waged independent battles. The elec­trical engineers have taken advantage of Moore’s law by utilizing the ever increasing supply of cheap transistors on a die to serve leading-edge apps in I/O circuits. On the electro-mechanical side of the battle, the designers of connectors and IC packages have incrementally leveraged new material and processes into interconnection elements, that while substantially traditional, perform better at higher speeds.

These printed circuit board and package structures translate directly into signal quality impediments. In particular, the de­vice-to-package solder bump and package-to-board solder ball interfaces are high impedance structures that create impedance compensation difficulties. In addition, signal layer transitions, in both the package and board, needed to route the signal from de­vice to device create significant low and high impedance changes in the signal path.

The chart in Figure 4 was generated by plotting the dielectric performance of a variety of commercially available printed circuit board laminate materials. There are many beneficial attributes of FR4 which continue to make it a favorite choice among system designers. Foremost among these attributes are cost and manu­facturing familiarity. Unfortunately, the performance of FR4 falls off dramatically as the data rate approaches 10 Gb/s. It is easy to see how the interconnection elements necessary to implement a 10G backplane create many challenges for the delivery of signals. To overcome signal quality issues, electrical engineers have im­plemented enhanced I/O electronics.

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Column Control DTX