Application Notes
Introduction
High-power amplifiers are a common building block of RF and microwave communication systems. Mobile phones, used by millions of users, contain high-power amplifier chips. Satellite systems and base-stations used for transmitting data depend on a multitude of solid-state or traveling-wave tube power amplifiers. Characterizing the performance of high-power amplifiers is a critical factor in the design and verification process.
Table of Contents
Power Budget Analysis and MW PNA Block Diagram
Step-by-Step Guide for Measuring a High Power Amplifier
Alternative High-Power Configurations
FAQ
Appendix A: Maximum Power Levels for PNA and PNA-L Network Analyzers
Appendix B: Understanding PNA measurements with an external reference
signal and source attenuator changes
Power Budget Analysis and MW PNA Block Diagram SourceR2B35
One of the main factors to consider in a high-power network analyzer measurement is the power-handling capability of the internal components of the network analyzer. High power levels can damage the network analyzer, and it is costly to repair the internal components of the network analyzer. In addition to damage level, compression level, and noise levels also have to be considered in a high-power setup.
The initial step in a high-power measurement is a calculation of the power budget or a power-flow analysis. In this section, we examine the block diagram of a PNA network analyzer, followed by two examples of power-flow analysis.
Figure 1 shows the block diagram of the 20 GHz E8362B1 MW PNA network analyzer. Table 1 lists the damage level for the components of the 20/40/50 GHz E8362/3/4B PNA. Damage and compression power levels for the 67 GHz E8361A PNA can be found in the Appendix. In general, we recommend that components not be operated near damage level and the power level be kept at least 3 dB (preferably 6 dB) below damage level. The user should be aware that the optimal level could be well below the damage level, as is the case with the receivers.
Why is the damage level listed at the test port +30 dBm, but +43 dBm for the coupler? Isn’t the coupler located right at the test port?
Yes. The coupler is right at the test port, but while the coupler can handle up to +43 dBm (<20 GHz), the bias-tees (which are located immediately after the coupler) have a damage level of +30 dBm.
Therefore if more than +30 dBm is applied to the test port, the bias-tees will be damaged. The receiver attenuators also have a +30 dBm damage level, but they can be protected with attenuation placed between the CPLR ARM and RCVR A IN jumpers. There is no jumper between the coupler and the bias-tee, so there is no way for a user to decrease the power between the coupler and the bias-tee. Thus the power at the test port should be limited to less than +30 dBm. If you want to take advantage of the high-power capabilities of the coupler, there are two options. One is to purchase an instrument without the bias-tees (and source attenuator, which is coupled with the bias-tees under option UNL). The second alternative is Keysight’s special MW PNA, E836x-H85. Special Option H85 adds the source attenuators, but not the bias-tees.
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