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Frequently Asked Questions B4655A FPGA Dynamic Probe for Xilinx

Data Sheets

The Keysight Technologies, Inc. FPGA dynamic probe provides greater real-time measurement productivity for logic analysis based validation of FPGAs and the surrounding system. The tool features:

  • Increased visibility — Traditional logic analyzer probes limit engineers to measuring signals at the periphery of the FPGA. With Keysight’s FPGA dynamic probe, engineers are able to measure up to 128 internal FPGA signals for each external FPGA pin dedicated to debug.
  • Faster probing changes — Keysight’s FPGA dynamic probe enables your design team to move probe points internal to the FPGA with a mouse click — without any design changes and without any changes to the timing of your design.
  • Automatic setup of the logic analyzer — The FPGA dynamic probe maps internal signal names from your FPGA design tool to your logic analyzer. The signal-naming capability of the Keysight FPGA probe eliminates mistakes and saves you the time it would take to manually set up signal and bus names and logic analyzer connections, providing a significant advantage over logic analyzers without this capability.

Q1 How do I create an ATC2 core?

Xilinx ChipScope Pro or EDK provides the capability to create an ATC2 core. You need Xilinx ChipScope Pro or EDK to create the ATC2 core and to merge it with your design. Using either of these tools, you can specify the parameters of the ATC2 core and specify which design signals go to the ATC2, making them available for real-time measurement.

Q2 How do I get an ATC2 core into my design?

Xilinx ChipScope Pro includes Core Inserter and Core Generator. Core Inserter puts the core into your FPGA design post synthesis. Keysight Technologies, Inc. recommends using Core Inserter. If you use Xilinx Core Generator or EDK, the tool instantiates your parameterized ATC2 as a black-box Verilog or VHDL unit. The synthesis tool puts the instantiated core into your design during the synthesis process.

Q3 What synthesis tools can I use to get the ATC2 core into my design?

ATC2 cores produced by Xilinx Core Generator or EDK are compatible with:

  • Exemplar Leonardo Spectrum
  • Synopsys Design Compiler
  • Synopsys Design Compiler II
  • Synopsys FPGA Express
  • Synplicity Synplify
  • Xilinx XST

Q4 Are there advantages to using Core Inserter versus Core Generator or EDK?

Yes. Core Inserter also produces a .cdc file. This is a small file listing the signal inputs to the ATC2 core. This file is used to automatically synchronize design signal names with logic analysis bus and signal names. Keysight recommends using Xilinx Core Inserter so you can take advantage of signal-name mapping. Xilinx has a stimulus core known as VIO. This core can only be created and placed in a design using Core Generator. For a single design that contains both a VIO core and an ATC2, Core Genera­tor must be used.

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