Building a Radar Target Simulator

Building a Radar Target Simulator

Using M3302A PXIe AWG and Digitizer Combination module to create a custom Transmitter-Receiver Tx-Rx simulator 

• Build a target simulator with a low-cost PXI-based instrument
• Simulate arbitrary settings such as frequency shift, delay, and reflection with signal processing in custom FPGA block
• Easily import data from model-based design tools and Xilink IP cores
• Apply to Radar target simulation and DRFM, as well as channel emulators, digital filters, delay devices, HILS, etc.

FPGA development Services

Keysight Technologies not only sells hardware and software products, but may also provide services according to customers’ requests for hardware implementation, software and application development. 

Example SW

Example software (source code) is available on request. This example shows integrating real-time processing between transmission channel and receiver channel. You can process signal input in the digitizer with a specified frequency shift and delay time and output it as an analog signal. In this example, a Doppler frequency of -300 kHz and a delay of 20 usec are specified, and the output is consistent with the settings even in the actual measurement. 

M3302A PXIe AWG / digitizer combo

• 2 channel 500MSa/s AWG and 2 channel 500MSa/s digitizer are combined in a single PXIe module with a shared FPGA
• User-programmable built-in FPGA (Xilinx Kintex 7)
• Skew between channels of 50 psec or less
• A shared FPGA enables less than 400 ns input to output latency
• Optional HVI technology allows synchronous phase coherent operation across multiple channel / chassis AWG and Digitizers combo units
• Combined with another PXI up-converter or downconverter to builds a target simulator and DRFM system at low cost

M3602A Graphical FPGA Development Environment (exclusive for M3xxxA modules) 

The user-customized area and the measurement area are clearly separated, allowing you to focus solely on the custom processing of AWG generation and Digitizer acquisition signals without having to implement the control of measurement. 

• The user-friendly graphical environment simplifies the development of custom DSP for the FPGA device enabling special modes of operation or new control structures
• Easily import FPGA codes and external IP
• VHDL, Verilog, and VIVADO/ISE projects, MATLAB/SIMULINK, Xilinx IP core 
• Fast one-click compilation 
• Reduced development time and compiling time together with hot programming enable dynamically-reconfigurable instruments.