Column Control DTX

x1149 Pin Constraints Feature

Technical Overviews

Software version 1.5.0 and below

One of the current features on the x1149 application (software version 1.5.0 and below) is the means to edit the test at the node level. Nodes can be set to Test, Hold High or Hold Low by selecting the Action required. The software will then drive the selected Action for the node throughout the test. Thus, if there is a receiving cell associated to the node, the expected result of the test will reflect the Action selected.

Boundary scan testing is commonly used for testing on interconnect nodes between two bidirectional boundary scan cells. When setting up the test for interconnect nodes, the x1149 application will automatically assign a designated driver (from one of the two bidirectional boundary scan cells) for that interconnect node and the other bidirectional boundary scan cell as a receiver.

In Figure 1, both U5.72 and U5.73 are bidirectional boundary scan cells and node CH17 is the interconnect node between them. The Frame Debugger window shows that the software has assigned U5.73 as the designated driver and U5.72 as the receiver. U5.73 will be receiving as well since it is a bidirectional boundary scan cell.

Challenges

Inaccurate BDSL file

An error on the designated driver can result in a failed test. This can occur if the BSDL file wrongly declares an input-only boundary scan cell as a bidirectional boundary scan cell. When this happens, the designated driver will not be able to send the output test pattern, and the receiving end will not be getting the expected values; resulting in a failure for that interconnect node.

That failed interconnect node will be commented, leading to test coverage loss.

FPGA chipset

Modified pin configurations in FPGA chipsets may also present a challenge for boundary scan testing. During programming, pin configurations can be modified on FPGA chipsets, altering the boundary scan cell configuration (from bidirectional cell to either output-only/input-only cell). Typically, only the pre-configuration BSDL file is available to the end-user. Thus, testing conducted without an accurate post-configuration BSDL file may result in failing nodes, since the assigned pins would be either be unable to drive or receive. Once again, the node is commented, leading to test coverage loss.

The conventional method to resolve the above-mentioned challenges is to manually edit the BSDL file by changing the boundary scan cell from bidirectional to output-only/input-only, regenerate the boundary scan test, run the test and verify if the pin is behaving per the changes made. This is a tedious and time-consuming process which may take up to several iterations before verification is completed. It will also require an engineer with sufficient knowledge on BSDL file syntax to make the changes. This process of verifying may also be prone to error.

Solution

The x1149 Pin Constraints feature is introduced to resolve the above-mentioned challenges, providing quick and easy access for modifying configurations down to the pin level. With the Pin Constraints feature, the x1149 software can modify the test code on the fly without the need to manually edit the BSDL file. It allows users to remove the driver or receiver of a pin, the software will then modify the test code so that the pin no longer drives or receives to/from that node. This can be achieved simply with just a few mouse clicks in the x1149 application, as shown below.

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Column Control DTX