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Expanding IEEE Std 1149.1 Boundary-Scan Architecture Beyond Manufacturing Test of PCBA

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Introduction IEEE Std 1149.1 (Boundary-scan)

The IEEE Std 1149.1 is an IEEE Standard for Test Access port and boundary-scan Architecture which was first released in 1990 to address the printed circuit board increasing density and manufacturing faults - such as open and shorts. The boundary-scan devices are specifically designed with internal shift registers placed between each device pin and the internal logic as shown in Figure 1. The shift registers are known as boundary-scan cells that are allowed to be controlled and observed at each input and output of the device pin. When these boundary-scan cells are connected together they form a data register chain called the Boundary Register and when the boundary-scan devices are connected, it is called the boundary-scan chain. These boundary-scan chain of boundary-scan cells provide the ability to drive/receive digital voltage levels (representing 0 and 1 values) to enable multiple forms of testing, programming, measurement and control that can be automated into special purpose test equipment, from just the 4-5 signals of the boundary-scan interface, called the Test Access Port ( TAP) which consist of Test Data Input (TDI), Test Data Output (TDO), Test Clock (TCK), Test Mode Select (TMS) and the optional Test Reset (TRST). The 1149.1 standard had gone through many improvements and enhancements. The last one in 2013 included major improvements to access function inside the device core which were only available previously through a Built-In Self-Test (BIST) execution. The next standards that garnered a lot of support from the network communication PCBA was the IEEE 1149.6 high-speed differential interconnects which was approved in 2005. It has just gone through ratification in 2015 to support the same PDL function in 1149.1-2013 but addressing the functions related to high speed differential.

The following topics will be discussed to show the expanding capability of the boundary-scan test system to extend beyond typical manufacturing test and address the coverage challenges of current and future PCBAs:

1. Boundary scan as part of the manufacturing test system – With the increasing density of the PCBA due to the proliferation of high speed differential signal especially on network communication and servers, the boundary-scan test becomes an integral part of ICT strategy to ensure the high test coverage and quality of every board. Boundary-scan also helps to balance the ICT system cost and at the same time retains the coverage needed, while ensuring those failed boards are repaired. Figure 2 shows a typical PCBA manufacturing line where the In-circuit test (ICT) system and functional test system are placed after the SMT line to capture structural and functional defects. Figure 3 also shows the stations where boundary-scan can be implemented as follows:

· Boundary Scan at In-Circuit Test (ICT) The ICT is the most favored manufacturing test system because of its ability to detect structural failures - such as opens, shorts, analog unpowered, and analog/digital powered testing including boundary-scan test with accuracy and speed. Modern ICT has the native software to execute boundary-scan test which includes both the IEEE Std 1149.1 and IEEE Std 1149.6 while those ICT that do not have the native boundary-scan software have an option to integrate a 3rd party boundary-scan box. Figure 

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