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Digital PLL Implementation in FPGA Using FPGAflow

Application Notes

Introduction

The Keysight Technologies, Inc. M3602A FPGA design environment simplifies the development of custom processing functions for the following PXIe modules: M3100A, M3102A, M3201A, M3202A, M3300A, M3302A with -FP1 (FPGA Programming) option enabled and one of the options -K32 (Kintex-7 K325T FPGA) or -K41 (Kintex-7 K410T FPGA) for the logic.

The user-friendly graphical environment simplifies the development of custom DSP for the FPGA device enabling special modes of operation or new control structures. This application note demonstrates the FPGA capabilities of Keysight M3300A AWG and digitizer PXIe combo module to perform closed-loop control using input and output channels in conjunction. In particular, this document demonstrates the implementation of a digital phase locked loop using the Keysight digital-PLL IP and a Keysight M3300A module. CH0 input is used as the feedback input, and the frequency correction is applied to CH0 output. The user selects the objective phase and frequency for the feedback signal (among other parameters), and the Digital-PLL will apply the necessary frequency corrections to the frequency input of the FuncGen_0 module in order to lock the feedback input to specified frequency and phase.

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