1GC1-8290 DC - 12 GHz Multi-Modulus Packaged Prescaler

Keysight 1GC1-8290

DC - 12 GHz Multi-Modulus Packaged Prescaler

1GC1-8290-BLK 7” diameter reel/500 each

1GC1-8290-TR1 bubble strip/10 each Data Sheet

Description

The 1GC1-8290 GaAs HBT MMIC prescaler offers broadband frequency translation for use in communications and EW systems incorporating high–frequency PLL oscillator circuits and signal–path down conversion applications. The prescaler provides multiple–modulus division and input signal pass–through capability as well as a large input sensitivity window, and low phase–noise. The 1GC1-8290 is available in either die form (1GC1-4021) or a 20–pin surface-mount QFN package (1GC1- 8290). In addition to the features listed above the component offers differential I/O, dual–output power mode plus an input disable pin to eliminate any false triggers or self–oscillation condition.

Applications

The 1GC1-8290 is designed for use in high frequency communications, microwave instrumentation and EW radar systems where low phase noise PLL control circuitry or broadband frequency translation is required.

Operation

The package is designed to operate when driven with either a single–ended or differential sinusoidal input signal over a 100 MHz to 12 GHz bandwidth. Below 300 MHz the prescaler input is "slew–rate" limited requiring fast rising and falling edge speeds to properly divide. The device will operate at frequencies down to DC when driven with a square–wave as long as the slew rate is greater than 0.18 V/nS or 10% to 90% edge speeds of ~ 3 nS. AC coupling at the RFin pin is recommended for most applications. The package can be operated from either a single positive or single negative supply. For positive supply operation VCC is nominally biased at any voltage in the +4.5 to +6.5 volt range with VEE (or VEE & VPwrSel) grounded. For negative bias operation, VCC is typically grounded and a negative voltage between – 4.5 to –6.5 volts is applied to VEE (or VEE & VPwrSel). The package will operate in pass– through mode (with unity divide modulus) or at any of four different divide ratios including 2, 4, 8, or 16 according to following table.

Several features are designed onto this prescaler

Dual–output power feature

Bonding both VEE and VPwrSel pins to either ground (positive bias mode) or the negative supply (negative bias mode), will deliver ~6.0 dBm [1.0 Vp–p] at the RF output port while drawing ~118 mA supply current. Eliminating the VPwrSel connection results in reduced output power and voltage swing, 0.0 dBm [0.5 Vp–p] but at a reduced current draw of ~96 mA resulting in less overall power dissipation. Note: VEE must always be bonded and VPwrSel must never be biased to any potential other than VEE or open–circuited.)

VLogic ECL pin

Under normal conditions no connection or external bias is required to this pin and it is self–biased to the on–chip ECL logic threshold voltage (VCC–1.34 V). The user can provide an external bias to this pin (1.5 to 1.2 volts less than VCC) to force the prescaler to operate at a system generated logic threshold voltage.

Input disable feature

By applying an external bias to this pin (more positive than V CC –1.34 V), the input preamplifier stage is locked preventing false trigger frequency division and self–oscillation frequency.

Input DC offset

Another method used to prevent false triggers or self–oscillation conditions is to apply a 20 to 100 mV DC offset voltage between the RFin and RFin ports. This prevents noise or spurious low level signals from triggering the divider.

Assembly techniques

Figures 4 and 5 show the package assembly diagram for single–ended or differential I/O operation through 12 GHz. For positive supply operation, VCC is typically biased to a positive voltage between +4.5 and +6.5 volts and VEE is grounded. For negative supply operation, VEE is typically biased between –4.5 to –6.5 volts and VCC is grounded. In either case the supply contact to the package bias pin must be capacitively bypassed (0.01 µF, recommended) to provide good bias stability, input sensitivity and low input power feedthrough. The bypass capacitor should be located as close as possible to the package pin.