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16860A Series Portable Logic Analyzers

Data Sheets

16860A Series

Portable Logic Analyzers

Introduction

Keysight’s 16860A Series is the industry’s highest-performance portable logic analyzer – providing you the best insight so you can solve your toughest digital debug challenges.

• High-speed state and timing with deep memory – Capture the most system activity (up to 128 Mb) at the highest resolution to identify the root cause of a problem and symptom widely separated in time

• Signal integrity – Quickly identify problem signals with simultaneous eye diagrams on all channels

• Probing and application support – Customize a system for your specific needs with a comprehensive set of probing options and application-specific software

• Upgradable – Purchase the capability you need now, then upgrade as your needs evolve 

Identify Problem Signals on All Channels Simultaneously

As timing and voltage margins continue to shrink, confidence in signal integrity becomes an increasingly vital requirement in the design validation process. Eye scan lets you acquire signal integrity information on all the buses in your design (and under a wide variety of operating conditions) in a matter of minutes. Identify problem signals quickly for further investigation with an oscilloscope. Results can be viewed for each individual signal or as a composite of multiple signals or buses.

Unleash the Power of a Logic Analyzer Plus an Oscilloscope

Seamless oscilloscope integration with View Scope

Easily make time-correlated measurements between Keysight logic analyzers and oscilloscopes. The time-correlated logic analyzer and oscilloscope waveforms are integrated into a single logic analyzer waveform display for easy viewing and analysis. You can also trigger the oscilloscope from the logic analyzer (or vice versa); automatically de-skew the waveforms; and maintain marker tracking between the two instruments. View Scope allows you to perform the following more effectively:

• Validate signal integrity

• Track down problems caused by signal integrity

• Validate correct operation of A/D and D/A converters

• Validate correct logical and timing relationships between the analog and digital portions of a design 

Connection

The Keysight logic analyzer and oscilloscope can be physically connected with standard BNC and LAN connections. Two BNC cables are connected for cross triggering, and the LAN connection is used to transfer data between the instruments. The View Scope correlation software is standard in the logic analyzer’s application software.

The View Scope software includes:

• Ability to import some or all of the captured oscilloscope waveforms

• Auto scaling of the scope waveforms for the best fit in the logic analyzer display

Debug, Verify, and Optimize DDR, LPDDR, and ONFi Memory Systems

The 16860A Series logic analyzers, in conjunction with memory specific probing solutions and B4661A Memory Analysis Software, provide a cost-effective platform for debugging, verifying and optimizing memory designs operating at ≤ 1400 MT/s. You can get a comprehensive view into your system’s memory operation with bus decode, transaction overview, compliance testing and performance analysis.

The 16860A Series supports Add/Cmd/Data state mode measurements for the following DDR and LPDDR memory families. For higher speed or channel count DDR/2/3, LPDDR/2/3, DDR4 and LPDDR4 memory applications, refer to Keysight’s U4164A logic analyzer module which is designed specifically for high-speed memory applications.

In addition, the 2.5 GHz timing mode provides a 3:1 ratio of sample rate to data rate so you can perform timing measurements on DDR/LPDDR devices with < 400 MHz clock rate/ < 800 Mb/s data rate. When a 16862A or 16864A logic analyzer is configured with the 10 GHz quarter channel timing option, the analyzer is capable of capturing Open NAND Flash Interface (ONFi) traffic. Analysis of captured ONFi traffic is provided through the Performance Analysis option (4FP/4NP/4TP) of the B4661A Memory Analysis Software.

Get Instant Insight into your Design with Multiple Views and Analysis Tools

When you want to understand what your target is doing and why, you need acquisition and analysis tools that rapidly consolidate data and provide insight into your system’s behavior.

16860A Series Logic Analyzer Specifications and Characteristics

State (synchronous) sampling mode

The state sampling clock mode specifies how the clock inputs are used for sampling. The availability of these state sampling clock modes depends on the state sampling option that you select.

• Primary - All pods sampled by the primary clock definition.

o In single clock mode, only the clock signal on Pod 1 can be used.

o In multiple clocks, either a single clock signal can be used, or a combination of clocks can be used.

• Dual sample - In the dual sample clock mode, you can capture two samples per clock edge with two different threshold offsets and separate sampling positions. These separate threshold offsets and sampling positions allow you to set independent thresholds and sampling positions for Read and Write in DDR/LPDDR captures and for Rising and Falling edge in general-purpose data captures. 

• Primary/secondary – Primary pod is sampled on Primary clock and secondary pod is sampled on secondary clock, but the captured data of both secondary and primary clocks is saved together when the primary clock occurs.

• Demux - Data being probed by one pod is demultiplexed into the logic analyzer memory that is normally used for two pods. The demultiplex mode uses the primary and secondary clocks to demultiplex the data.

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