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ABCs of Writing a Custom Boundary Scan Test

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ABCs of Writing a Custom

Boundary Scan Test

Article Reprint

ABCs of Writing a Custom Boundary Scan Test

Sample vectors and code for expanding test coverage.

Boundary scan or JTAG (Joint Test Action Group) is an IEEE Standard 1149.1 that defines the test access port and boundary scan architecture of digital integrated circuits. Boundary scan is a test technique that involves devices designed with shift registers placed between each device pin and the internal logic. Each shift register is called a boundary scan cell. These boundary scan cells allow control and observation of what happens at each input and output pin. When these cells are connected together, they form a data reg-ister chain called the boundary register.

Boundary scan has become an important limited access solution for printed circuit board assemblies, and includes tests for digital inte-grated circuits interconnection, as well as testing and programming digital devices such as flash, EEPROM and serial peripheral interface (SPI) devices. Boundary scan also has the capabil-ity to execute other tests, as defined in the BSDL (Boundary Scan Description Language), including private instructions which support internal func-tions of a boundary scan device, such as built-in self-test (BIST).

The boundary scan operation is controlled by a test access port (TAP), the control system of a boundary scan device. The TAP controller of a boundary scan device consists of a 16-state machine. The flow of data to the instruction register (IR) and the data register (DR) is controlled by the test mode select (TMS) with a 0 or 1 bit to move from one state to another state, while the TCK synchronizes the 16-state machine operation. The TAP controller state diagram shows the sequence of any boundary scan test through the TAP controller, and applies to components that comply with IEEE 1149.1.

Each position in the DR and IR columns repre-sents a state of the TAP controller of the 16-state machine that controls each boundary scan device. The DR column comprises data instructions that, when passed through, affect the operation and contents of the data register. The DRs include bypass register, a mandatory register that all boundary-scan-compliant devices must contain. Either that or it will need to have the optional IDCODE, USERCODE registers, or a designer-specified register that complies with the IEEE standard.

The IR column comprises data instructions that, when passed through, affect the operation and contents of the IR, a mandatory component of every boundary scan device. The success of boundary scan in the manu-facturing test environment depends largely on the availability of ATPG (Automatic Test Program Generation), which can help test engineers develop and generate the boundary scan tests.

The following are examples of automatically-generated boundary scan tests:

  1. Infrastructure test – Verifies that the TAP of all boundary scan devices in the chain operate properly. If this test fails, testing stops and power is disabled from the board. This test is a preamble to all other boundary scan tests; it is an integral part of each test and is executed before each test runs.
  2. Interconnect test – Verifies the boundary scan device pins 1149.1 and 1149.6 interconnec-tion with other boundary scan device pins.
  3. Buswire test – The bus wire test looks for opens on all the bussed boundary scan devices test developed on PC boundary scan tool can be executed at the ICT manufacturing test stage, if inte-grated into ICT.
  • Integration of PC boundary scan tool in ICT during volume manufacturing will shorten development time, hence improving time-to-market.


Not all SSDs are testable using ICT. Due to consumer demands for smaller, faster and longer bat-tery life devices, the size of every component in electronics devices is also shrinking, including the printed circuit board.

Pc Boundary Scan Test

  • PC boundary scan test can involve the following:
  • Boundary scan interconnect and buswire test. Although there is only one boundary scan device, the interconnect and buswire will still be able to test a few pins that are interconnect or pins that have a self-monitoring boundary scan cell.
  • Boundary scan pull-up/pull-down resistor.
  • Boundary scan silicon nail: Tests interconnection between NAND controller and NAND flash devices.
  • Loopback test between SATA/PCIe and NAND flash controller.
  • Cover-Extend test for non-bound-ary scan devices and connectors.

In some cases programming is needed for SEEPROM, SPI flash and PIC devices.

There are limitations with using only the benchtop boundary scan tool, though. One is the issue of not being able to perform unpowered and powered tests, as an ICT system can. To resolve these limitations, a dedi-cated SSD manufacturing test solu-tion has been developed to perform both ICT and boundary scan test during volume manufac-turing testing.

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