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DesignCon 2014

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Abstract

 

Large port count (>100) Touchstone® v2.0 S-Parameter data formats with per port reference impedances are essential in designing the next generation of memory interconnects. Using DDR4 as an example this paper shows how Touchstone v1.0 format limitations can lead to erroneous or inaccurate results for SI and PI co-simulations and how they can be overcome using the new v2.0 format. In addition to reliable channel models, one also needs accurate representation of the memory controllers and memory modules. To simulate SSN, Power Aware IBIS v5.0 models are required. This paper will demonstrate the accuracy and efficiency of such models by examining a few examples. These models, combined with the interconnect models, can then be used in a transient (SPICE) simulator to analyze SSN and its effects on the design. Such an analysis allows one to identify problem areas, debug issues and optimize the design to meet specifications in a timely manner.

 

Author(s) Biography

 

Romi Mayder is currently the Senior Manager of Transceivers and IOs in the Technical Marketing Department at Xilinx, Inc. Prior to joining Xilinx, Mr. Mayder worked as a consultant specializing in silicon die level signal and power integrity. He also consulted in the field of design and fabrication of advanced package technologies, including stacked silicon interconnect. Mr. Mayder has been employed by two companies in the Test and Measurement industry, Agilent Technologies and Anritsu (Wiltron) Company, where he specialized in microwave and millimeter wave microelectronic circuit design and fabrication. Additionally, Mr. Mayder has over 10 years of experience in semiconductor process technologies including photolithography, ion implantation, plasma enhanced chemical vapor deposition, dielectric sputtering, and chemical mechanical polishing of silicon wafers. Mr. Mayder received his Bachelor of Science degree in Electrical Engineering and Computer Science from the University of California at Berkeley in 1992. Mr. Mayder has published 25 patent applications in the fields of signal and power integrity as well as semiconductor process technologies.

 

Raymond Anderson is Senior Signal Integrity Staff Engineer at Xilinx. His current activities include package development and  modeling and simulation of high-speed IO and power distribution networks for FPGAs.  He holds a BSCS degree from National University. Prior to his current Xilinx position he has held positions at California Microwave, Equatorial Communications, GTE Spacenet and Sun Microsystems. His background includes microwave amplifier design, development of satcom ground station systems, CAD software development and both PCB and package level signal integrity work. He has published 5 signal integrity related papers at various IEEE conferences and holds 8 patents in the signal integrity field.

 

Nilesh Kamdar is Senior Applications Engineer at Agilent Technologies. He has over 14 years of experience working on high frequency and high speed digital design. Mr. Kamdar managed the Simulation Architecture team at Agilent EEsof in his previous role. He received his Masters of Science degree in Electrical Engineering from Utah State University in 1999.

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