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J-BERT M8020A High-Performance BERT Ver. 9.0

Data Sheets

J-BERT M8020A High-Performance BERT

Master your next designs

Introduction

The high-performance Keysight Technologies J-BERT M8020A enables fast and accurate receiver characterization of single and multi-lane devices running up to 16 or 32 Gb/s.

The high-performance Keysight Technologies J-BERT M8020A enables fast and accurate receiver characterization of single and multi-lane devices running up to 16 or 32 Gb/s.

Key Features

• Data rates up to 8.5 and 16 Gb/s expandable to 32 Gb/s

• 1 to 4 BERT channels in a 5-slot AXIe chassis

• Integrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, sinusoidal level interference (common-mode and differential-mode), SSC (triangular and arbitrary, residual) and Clock/2

• 8 tap de-emphasis, positive and negative

• Integrated and adjustable ISI

• Interactive link training for PCI Express 8 GT/s and 16 GT/s

• Interactive link training for USB 3.0 and USB 3.1

• DUT RX / BERT TX equalizer negotiation for 10GBASE-KR

• Built-in clock recovery and equalization

• All options and modules are upgradeable

Applications

The J-BERT M8020A is designed for R&D and test engineers who characterize and verify compliance of chips, devices, boards and systems with serial I/O ports up to 16 Gb/s and 32 Gb/s in the consumer, computer, mobile computing, datacenter and communications industry.

The J-BERT M8020A can be used to test popular serial bus standards, such as PCI Express®, SATA/SAS, DisplayPort, USB Super Speed, MIPI® M-PHY®, SD UHS-II, Fibre Channel, QPI, memory buses, backplanes, repeaters, active optical cables, Thunderbolt, 10/40 GbE/SFP+/QSFP, 100GbE/CFP2.

M8000 Series of BER Test Solutions

Simplified time-efficient testing is essential when you are developing next-generation computer, consumer, or communication devices.

The Keysight M8000 Series is a highly integrated BER test solution for physical layer characterization, validation, and compliance testing.

With support for a wide range of data rates and standards, the M8000 Series provides accurate, reliable results that accelerate your insight into the performance margins of high-speed digital devices.

Shift into high gear with the M8000 Series and take the design verification express lane.

• Multi-channel applications

• Interactive link training

• Analyzer equalization and clock recovery

• Expandable to higher data rates up to 32 Gb/s

• Higher integration: 16G BERT with 1-4 channels, jitter, de-emphasis

J-BERT M8020A High-Performance BERT

Enabling fast, accurate receiver characterization of single- and multi-lane devices running up to 16 or 32 Gb/s

Highest Level of Integration for Streamlined Test Setups

With J-BERT M8020A all receiver (RX) test capabilities are built-in: jitter sources, common and differential-mode level interference, and de-emphasis to emulate the transmitter (TX) of the device under test (DUT). In addition, M8020A provides a built-in reference clock multiplier for synchronization of the BERT pattern generator with the DUT’s reference clock which can carry spread spectrum clocking (SSC). On the analyzer side, a built-in equalizer re-opens closed eyes and a clock recovery with adjustable loop bandwidth enables repeatable BER measurements.

With this high level of integration, a receiver test set-up with M8020A is now much easier to connect and more robust. Set up and debug time is shortened, calibration is simpler, and the frequency of recalibration is lower, resulting in more efficient use of overall test time.

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