x1149 Boundary Scan Analyzer

Better Coverage, Better Diagnostics, Best-in-Class Usability

Boundary scan has become an indispensable technology as engineers like you face

increasing test challenges. Keysight Technologies, Inc. is proud to introduce the new x1149 Boundary Scan Analyzer — bringing the best of our technology and vast test

experience — to your workbench!

The x1149 boundary scan analyzer is a versatile yet simple to use tool that helps you all the way through from your design validation and prototyping phase to pre-ramp up and mass manufacturing.

Key features

• Cover-Extend Technology (coverage on non-scan components)
• In-system programming for CPLD/FPGA
• Integrated scan-path linker
• Actionable pin-level failure reporting
• Built-in remote access via Ethernet
• 22.5 MHz test clock
• 4 dedicated TAP/IO ports

Cover-Extend Technology (CET)

x1149 is the only bench top solution in the market that offers Cover-Extend Technology (CET). CET is a patented and award-winning* innovation that combines boundary scan and capacitive-coupled sensing technology. (See inset on how it works.)

• Provides easy coverage
• Extends coverage for non-scan component
• No extra cost working with digital plug-in modules for connectors
• No hassle writing libraries
• Based upon Vectorless Test Extended Performance (VTEP), an industry-proven technology
• Auto-debug

Better Coverage

In-System Programmer

Programming CPLDs and FPGAs has never been easier. With a built-in Standard Test And Programming Language (STAPL) player, programming these devices is as a simple as executing a file.

The software accepts any of these file formats: STAPL, SVF, JAM and JBC which it takes and executes using the built-in engine. You can change the files as you go, making the implementation of In-system Programming simple while leveraging upon your efforts upstream.

Integrated Scan Path Linker

With your integrated scan path linker, you have the power to maximize test coverage on interconnect nodes between scan chains by linking them into one; test coverage that you won’t otherwise have if the chains were treated separately. During your debug, you may decide to keep the chains separate and break up a linked-up chain – the flexibility is yours!

IEEE 1149.6

Cover today’s high speed digital networks such as AC-coupled differential lines. Your x1149 unit already comes with support for the IEEE 1149.6 standard.

Shorted Capacitors

With the implementation of IEEE 1149.6 on advanced digital networks, you have the additional coverage on shorted coupling capacitors. The test effectiveness depends on the ability to properly manage the timing of state changes in relation to the time constant of the AC-coupled

capacitor. All this is done automatically for you in the background.

Pull-up/Pull-down Resistors

Modern board designs are peppered with either pull-up resistors or pull-down ones for purposes of termination, voltage divide, logic tie, etc. x1149 gives users coverage on these components as a default feature using the network of boundary scan cells to determine their presence.

Silicon Nails

Got non-boundary-scan devices? No problem. Silicon nails test, or sometimes called cluster test, uses the boundary scan cells in the scan chain as drivers and/or receivers to stimulate non-boundary scan devices which may include memory devices. Silicon nails increases your test coverage as you are no longer confined to just IEEE 1149.x compliant devices.

Better Diagnostics

Actionable Failure Report

Failure reports enable corrective actions. The x1149 produces actionable pin-level failure reports that highlights defect locations that can be understood by everyone – encouraging faster resolution and reduces miscommunication especially when dealing across geographies.

Buswire Test

Board defects that are detected can either originate from the driving or receiving end of a net or both.

Buswire test ensures that nets that have bidirectional boundary scan cells are exercised both ways to give better diagnostic resolution to detected defects.

Voltage Monitoring

Ability to monitor voltages is critical not only as a debug tool but as a foundation of subsequent structural tests. It gives you control and ensures lines that are supposed to be held continue to do so even in between tests. This avoids false impressions of failures that could be due to improper power rather than defective parts.

Coverage Report

Test coverage report tells you how effective your tests are and how much test coverage you are getting before you commit your board design to volume production.

Superior Signal Quality

Signal quality is increasingly important as logic levels trend lower. To prevent unintended state transitions leading to false calls, you need to have better control of your I/Os and have them respond to the way you want them to.

Best-in-class User Interface

More than ever before, usability plays a critical role in the effectiveness of the tools we use. User interfaces have to be intuitive and help to intelligently assist you with your tasks. x1149 presents a user interface (UI) that is best in class.

Automatic Scan Chain Detector

One of the key tasks when working with boundary scan is validating the scan chain. The UI comes with the ability to identify the potential scan chain! This is powerful especially for complex and long chains. The software is able to analyze the board topology, even taking into consideration components between boundary scan devices to present to you how the scan chain looks like.

Get the right BSDL

Another key task is ensuring you have the right Boundary Scan Description

Language (BSDL) files. The UI has a built-in BSDL syntax checker and compiler. It is able to automatically look for BSDL files in your depository folder without needing you to explicitly point to it. You can even port over BSDL files from a known good project – just by importing that one project name; and not the dozens of BSDL file names. It is cleaner, easier and saves you time.

Best-in-class User Interface

Debug Tools

You have a number of debug tools at your disposal. There is the Auto-Adjust that helps you automatically tweak various parameters like the slew rates, TCK speed, voltage offsets for TDI/TDO, etc. to find the optimum setting for your UUT. The Frame Debugger lets you do a deep dive debug if you want to analyze frame by frame. The Cover-Extend Test (CET) auto debug tool helps to automatically set the thresholds while maintaining the level of test quality (i.e. Cpk) that you want.

Other examples include a BOM parser, waveform viewer and other efficiency features like ability to do side-by-side code comparison, filtering of node names to ease viewing and selection and much more.

Language Localization

The standard English user interface comes with a Simplified Chinese option. With our translation matrix, additional languages can be added. As your operations span the globe, having local language support eases your daily tasks.