Data Sheets
Description
R&D and test engineers who need to characterize serial interfaces of up to 32 Gb/s can use the M8061A 2:1 Multiplexer with optional de-emphasis to extend the rate of J-BERT M8020A and J-BERT N4903B pattern generator. For the most accurate receiver characterization results, the M8061A provides four calibrated de-emphasis taps, which can be extended to eight taps, built-in superposition of level interference and Clock/2 jitter injection. The N4877A 32G CDR and de-multiplexer can be used to complement the setup for the analyzer side. The M8061A is a 2-slot AXIe module that can be controlled via USB from the user interfaces of J-BERT M8020A as well as J-BERT N4903B. Typical applications that require testing at data rates up to 32 Gb/s are: Optical transceiver such as 100GBASE-LR4, -SR4 and -ER4, 32G Fibre Channel SERDES and chip-to-chip interfaces, such as OIF CEI Backplanes, cables, repeaters, such as 100GBASE-KR4
Key features
32 Gb/s BERT setup with J-BERT M8020A and M8061A
To characterize receivers that operate up to 32 Gb/s, the M8061A multiplexer can be used with J-BERT M8020A and N4877A as a 32 Gb/s high-performance BERT. It provides excellent intrinsic jitter performance, integrated and calibrated jitter injection capabilities to stress receivers under test, 4/8-tap de-emphasis to emulate transmitter de-emphasis and to compensate for losses in the channel and a tunable CDR to enable full sampling BER and jitter tolerance measurements up to 32 Gb/s. A powerful pattern sequencer allows generating algorithmic PRBS as well as memory pattern sequences. Up to two 32 Gb/s channels can be configured for crosstalk testing and PAM-4 pattern generation.
Extend the data rate of J-BERT N4903B up to 28.4 Gb/s
The M8061A multiplexer can be used to extend the data rate of the J-BERT N4903B pattern generator to 28.4 Gb/s as shown below. All jitter injection capabilities of J-BERT N4903B are available also with M8061A as it is transparent to the jitter from N4903B. When clean signals are required, it can operate with a clean clock source to further lower its intrinsic jitter. A USB connection between J-BERT N4903B and M8061A allows controlling all parameters of the M8061A via the user interface of J-BERT N4903B.
De-embed signal degradations caused by the test set up and fixtures using the de-emphasis
Minimizing the influence of the test environment is a challenge especially if bit rates exceed 20 Gb/s. To de-embed the signal degradations caused by cables, test fixtures, adapters, etc. The de-emphasis technique is commonly used. M8061A is the only instrument that offers up to 8 tap de-emphasis up to 32 Gb/s, allowing compensation of signal degradations in very fine steps.
Emulate channel loss with negative de-emphasis
Channel losses can be emulated by using the negative de-emphasis funcion of the M8061A. See figure 2. The post-cursor taps can be used to emulate channel losses for higher frequencies. As a guideline: with the 5 post-cursor taps of M8061A loss frequencies above f / 5 can be emulated; for example for a data rate of 28 Gb/s, f equals 14 GHz, and f/5 corresponds to 2.8 GHz. See figure 7.
Accurately characterize receivers up to 32 Gb/s
Many SERDES, backplane, cables and optical receivers operate at data rates of 25 Gb/s and beyond. To characterize the receiver tolerance against jitter, cross-talk, level interference, and voltage sensitivity the M8061A can be used as 2:1 multiplexer to extend the pattern generator data rate of the J-BERT M8020A up to 32 Gb/s and J-BERT N4903B up to 28.4 Gb/s. But it can also be used to provide calibrated jitter, because it is transparent to the calibrated jitter from J-BERT and offers additional Clock/2 jitter injection. Built-in interference superposition (common-mode and differential mode) eliminates the need for external adders.
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