DDR4 Memory Bus Protocol Analysis

Achieve straightforward and reliable DDR4 DIMM bus analysis at 3300MT/s and DDR4 SO-DIMM analysis at 2400MT/s

The Double Data Rate 4 (DDR4) memory bus introduces changes in the communica­tions protocol and increases the clock frequencies and data transfer rates for Dual Inline Memory Modules (DIMMs). These developments present new challenges in the design and debug of computer motherboards and DIMMs or SO-DIMMs (Small Outline DIMMs) incorporating the new DDR4 technology, especially in the area of protocol analysis and verification.

The FuturePlus FS2510AB DDR4 DIMM and FS2512 DDR4 SO-DIMM interposers provide a mechanical, elec­trical and software interface between the Keysight Technol­ogies U4154B logic analyzer and the DDR4 connector. The FS2510AB and FS2512 are used to design and debug computer motherboards and DIMMS or SO-DIMMs incorporating DDR4 technology.

The FS2510AB and FS2512 protocol-decode software translates acquired signals into easily understood bus transactions, at the full bus speed. The Keysight logic analyzer provides extensive triggering and store qualification features. The FS2510AB DIMM interposer can be configured to perform state analysis of Reads or Writes, or both Reads and Writes, at up to 3300 MT/s. The FS2512 SO- DIMM interposer can be configured to perform state analysis of Reads or Writes, or both Reads and Writes, at up to 2400 MT/s.

• Quick, easy connection between DDR4 DIMM or SO-DIMM connectors & Keysight U4154B logic analyzers
• Complete, accurate 3300MT/s state and timing analysis up to 12.5 GHz
• Compatible with 284 & 288 pin DDR4 DIMM’s and 260 pin SO-DIMM’s
• All signals are probed passively, does not require U4201A cables.
• Supports registered, unbuffered, and large register (LR) DIMMs
• Burst sizes of 2, 4, or 8 supported.
• Monitors writes only, reads only, or writes and reads simultaneously.
• Quick and easy setup using Keysight EyeScan with 5 ps/5 mV resolution

DDR4 Memory Protocol Analysis and Compliance Verification

The DDR4 protocol decode software exe­cutes in the logic analyzer. The user selects attributes such as Burst length, CAS and Additive Latency, and Chip Selects to decode the key DDR bus signals. The logic analyzer displays the transaction type, address, data and command conditions and user-defined symbols. User-selectable post-processing filters allow the acquired data for different types of transactions to be displayed in different colors.

As timing and voltage margins continue to shrink, confidence in signal integrity be­comes an increasingly vital requirement of the design verification process. Keysight’s EyeScan lets you quickly acquire comprehensive signal integrity information on the DDR4 bus in your design, and can provide measurements with 5 ps of resolution.

The FS2510AB and FS2512 plug directly onto the Keysight logic analyzer module, maximizing the quality of the connection to the system under test. The FuturePlus DDR4 interposers, when used with an Keysight Technologies logic analyzer, allow you to achieve straight forward and reliable protocol analysis of your DIMM and SO-DIMM designs.