Column Control DTX

B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation

Data Sheets

Introduction

Accelerate your time to insight using the B4623B bus decoder for LPDDR, LPDDR2, LPDDR3, or LPDDR4 debug and validation. The B4623B provides complete protocol decode of memory transactions using a Keysight logic analyzer as the analysis execution engine. The B4623B protocol-decode software translates acquired signals into easily understood bus transactions showing associated data bursts, for all LPDDR/2/3/4 data rates. Valid Read and Write commands are decoded to include Row and Column Addresses and the complete data burst associated with the command. The B4623B bus decode software anticipates key system attribute inputs (Burst length, CAS Latency and CAS Write Latency, Chip Selects) from default LPDDR/2/3/4 probing configurations and/or DDR Setup Assistant tool to accelerate decode of LPDDR/2/3/4 bus signals.

Key features and benefits:

Decodes LPDDR, LPDDR2, LPDDR3, or LPDDR4 acquired traces on Keysight logic analyzer or off-line

Displays commands, protocol transaction type, physical/row/column/bankaddresses, and data in the listing viewer

Data bursts are associated and displayed with appropriate Read and Writetransactions

Data is displayed at any level of detail from protocol to binary

Anticipates key system attribute inputs from default probing configurations and/or DDR Setup Assistant tool

Allows user input to customize decoder properties

 

The properties button on the B4623B icon allows the selection of memory variables. Typically, preferences are filled out for the user in default configurations for specific LPDDR/2/3/4 probes and by the DDR Setup Assistant software tool*, as it helps walk the user through state mode setups.

Refer to your logic analyzer module data sheet or specific LPDDR/2/3/4, probing solution for logic analyzer module configurations.

Default configurations for B4623B bus decoder for LPDDR/2/3/4 debug and validation are loaded for recommended E5406A Soft Touch Pro footprints, when the B4623B SW is installed.

For custom embedded applications, where changes are made to default configurations, refer to on-line help in the logic analyzer software application for details on the B4623B bus decoder label requirements. For new embedded application configurations, Keysight recommends using the DDR Configurator Creator tool to create a configuration for your unique embedded system. DDR Configurator Creator tool is provided at no cost with version 5.80 and higher software.

Users of the B4623A LPDDR, LPDDR2 bus decoder can upgrade to the B4623B bus decoder for LPDDR/2/3/4 debug and validation by ordering the B4621U.

B4623U upgrade from B4623A bus decoder for LPDDR, LPDDR2 to B4623B bus decoder for LPDDR/2/3/4 requires a prior license for B4623A.

The B4623B bus decoder for LPDDR/2/3/4 debug and validation operates with multiple Logic Analyzers from Keysight Technologies. Logic analyzer selection criteria includes: logic analyzer specifications and characteristics, maximum DDR technology data rate, and minimum data valid windows of the data eyes at the logic analyzer probe point.

Keysight’s 4.0GT/s U4154B or U4154A logic analysis modules are recommended for all LPDDR, LPDDR2, LPDDR3, or LPDDR4 configurations.

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Column Control DTX